| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 479 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
487 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
494 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
510 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
708 // Custom legalize GlobalAddress nodes into LO/HI parts.
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 32 Lo, ///< Low address component (lower 16)
|
| SPUISelLowering.cpp | 487 case SPUISD::Lo: return "SPUISD::Lo";
616 && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 42 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 172 // addiu $t9, $t9, %lo(NewVal)
179 int Lo = (int)(NewVal & 0xffff);
182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
219 int Lo = (int)(EmittedAddr & 0xffff);
222 // addiu t9, t9, %lo(EmittedAddr)
226 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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| MipsISelLowering.h | 37 // No relation with Mips Lo register
38 Lo,
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| MipsLongBranch.cpp | 262 int64_t Lo = SignExtend64<16>(Offset & 0xffff);
272 // addiu $at, $at, %lo($tgt - $baltgt)
293 .addReg(Mips::AT).addImm(Lo);
312 // daddiu $at, $at, %lo($tgt - $baltgt)
345 .addReg(Mips::AT_64).addImm(Lo);
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| MipsISelDAGToDAG.cpp | 148 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
174 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
188 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
204 // 1. addiu $2, $2, %lo(_gp_disp)
335 // addiu $2, $2, %lo($CPI1_0)
339 // lwc1 $f0, %lo($CPI1_0)($2)
340 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
369 SDNode *Lo = 0, *Hi = 0;
375 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
377 InFlag = SDValue(Lo, 1)
[all...] |
| MipsISelLowering.cpp | 62 case MipsISD::Lo: return "MipsISD::Lo";
330 // multHi/Lo: product of multiplication
331 // Lo0: initial value of Lo register
383 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
403 // multHi/Lo: product of multiplication
404 // Lo0: initial value of Lo register
456 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
505 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64
[all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 138 uint64_t Lo = readInt();
140 uint64_t Result = Lo | (Hi << 32);
|
| MathExtras.h | 223 // leading zeros in hi portion plus all bits in lo portion
226 // get lo portion
227 uint32_t Lo = Lo_32(Value);
229 Count = CountLeadingZeros_32(Lo)+32;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
60 Hi, Lo,
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| PPCISelDAGToDAG.cpp | 114 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
127 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
789 unsigned Lo = Imm & 0xFFFF;
794 // Just the Lo bits.
795 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
796 } else if (Lo) {
800 // And Lo bits.
802 SDValue(Result, 0), getI32Imm(Lo));
824 if ((Lo = Remainder & 0xFFFF)) {
826 SDValue(Result, 0), getI32Imm(Lo));
[all...] |
| PPCISelLowering.cpp | 501 case PPCISD::Lo: return "PPCISD::Lo";
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
30 // These routines assume that the Lo/Hi part is stored first in memory on
31 // little/big-endian machines, followed by the Hi/Lo part. This means that
32 // they cannot be used as is on vectors, for which Lo is always stored first.
34 SDValue &Lo, SDValue &Hi) {
36 GetExpandedOp(Op, Lo, Hi);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeDAG.cpp | 396 SDValue Lo = Val;
401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
528 SDValue Lo, Hi;
530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
678 if (TLI.isBigEndian()) std::swap(Lo, Hi)
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 237 SDValue Lo, Hi;
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
243 std::swap(Lo, Hi);
248 JoinIntegers(Lo, Hi));
[all...] |
| LegalizeVectorTypes.cpp | 459 SDValue Lo, Hi;
475 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
477 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
478 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
479 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
480 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
481 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
482 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
483 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
484 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | 122 SDValue Lo, Hi;
127 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
132 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
137 std::swap(Lo, Hi);
139 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
149 Lo = Val;
151 std::swap(Lo, Hi);
155 DAG.getConstant(Lo.getValueType().getSizeInBits(),
157 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
2410 uint64_t lo = (lowValue - lowBound).getZExtValue(); local
[all...] |
| /external/skia/src/core/ |
| SkMath.cpp | 102 uint32_t lo = C + (B << 16); local
103 int32_t hi = A + (B >> 16) + (lo < C);
106 hi = -hi - Sk32ToBool(lo);
107 lo = 0 - lo;
112 SkASSERT(((int32_t)lo >> 31) == hi);
114 return lo;
122 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
123 int roundBit = (lo >> (shift - 1)) & 1;
124 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 573 SDValue Lo(Hi.getNode(), 1);
574 SDValue Ops[] = { Lo, Hi };
590 SDValue Lo(Hi.getNode(), 1);
591 SDValue Ops[] = { Lo, Hi };
687 SDValue Lo(Hi.getNode(), 1);
688 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
695 SDValue Lo(Hi.getNode(), 1);
696 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
706 SDValue Lo(Hi.getNode(), 1);
711 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi)
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | 702 Expr *Lo = CS->getLHS();
704 if (Lo->isTypeDependent() || Lo->isValueDependent()) {
715 CheckConvertedConstantExpression(Lo, CondType, LoVal, CCEK_CaseValue);
720 Lo = ConvLo.take();
724 LoVal = Lo->EvaluateKnownConstInt(Context);
728 Lo = DefaultLvalueConversion(Lo).take();
729 Lo = ImpCastExprToType(Lo, CondType, CK_IntegralCast).take()
[all...] |
