| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc();
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc();
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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| Thumb1RegisterInfo.cpp | 241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
291 const MCInstrDesc &MCID = TII.get(ExtraOpc);
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
360 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
361 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
|
| MLxExpansionPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc();
141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
144 unsigned Opcode = MCID.getOpcode();
278 const MCInstrDesc &MCID = MI->getDesc();
286 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
296 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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| Thumb2ITBlockPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc();
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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| ARMBaseRegisterInfo.cpp | [all...] |
| Thumb2SizeReduction.cpp | 192 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
193 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
512 const MCInstrDesc &MCID = MI->getDesc();
513 if (MCID.hasOptionalDef() &&
514 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
656 const MCInstrDesc &MCID = MI->getDesc();
657 if (MCID.hasOptionalDef()) {
658 unsigned NumOps = MCID.getNumOperands();
684 unsigned NumOps = MCID.getNumOperands();
686 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
28 if (!MCID)
94 const MCInstrDesc &MCID = TII.get(Opcode);
96 isLoad = MCID.mayLoad();
97 isStore = MCID.mayStore();
99 uint64_t TSFlags = MCID.TSFlags;
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| PPCInstrInfo.cpp | 433 const MCInstrDesc &MCID = get(Opc);
434 if (MCID.getNumOperands() == 3)
435 BuildMI(MBB, I, DL, MCID, DestReg)
438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
129 if (MCID == NULL) {
133 unsigned idx = MCID->getSchedClass();
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
185 assert(MCID && "The scheduler must filter non-machineinstrs");
186 if (DAG->TII->isZeroCost(MCID->Opcode))
193 unsigned idx = MCID->getSchedClass();
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| PeepholeOptimizer.cpp | 415 const MCInstrDesc &MCID = MI->getDesc();
416 if (MCID.getNumDefs() != 1)
435 const MCInstrDesc &MCID = MI->getDesc();
438 if (MCID.getNumDefs() != 1)
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| ExecutionDepsFix.cpp | 455 const MCInstrDesc &MCID = MI->getDesc();
457 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
| TargetInstrInfoImpl.cpp | 63 const MCInstrDesc &MCID = MI->getDesc();
64 bool HasDef = MCID.getNumDefs();
128 const MCInstrDesc &MCID = MI->getDesc();
129 if (!MCID.isCommutable())
133 SrcOpIdx1 = MCID.getNumDefs();
163 const MCInstrDesc &MCID = MI->getDesc();
168 if (MCID.OpInfo[i].isPredicate()) {
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| RegAllocFast.cpp | 850 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| MachineVerifier.cpp | 745 const MCInstrDesc &MCID = MI->getDesc();
746 if (MI->getNumOperands() < MCID.getNumOperands()) {
748 *OS << MCID.getNumOperands() << " operands expected, but "
789 const MCInstrDesc &MCID = MI->getDesc();
791 // The first MCID.NumDefs operands must be explicit register defines
792 if (MONum < MCID.getNumDefs()) {
793 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
800 } else if (MONum < MCID.getNumOperands()) {
801 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
805 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1))
[all...] |
| RegisterCoalescer.cpp | 723 const MCInstrDesc &MCID = DefMI->getDesc();
724 if (MCID.getNumDefs() != 1)
730 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
[all...] |
| TwoAddressInstructionPass.cpp | 394 const MCInstrDesc &MCID = MI.getDesc();
396 ? MI.getNumOperands() : MCID.getNumOperands();
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 239 MCInstrDesc MCID = MI->getDesc();
240 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
|
| MipsInstrInfo.cpp | 177 const MCInstrDesc &MCID = get(Opc);
178 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 152 const MCInstrDesc &MCID = MI->getDesc();
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 65 const MCInstrDesc *MCID; // Instruction descriptor.
98 /// MCID NULL and no operands.
108 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
113 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
118 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
125 const MCInstrDesc &MCID);
254 const MCInstrDesc &getDesc() const { return *MCID; }
258 int getOpcode() const { return MCID->Opcode; }
326 return hasProperty(MCID::Variadic, Type);
332 return hasProperty(MCID::HasOptionalDef, Type)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 305 const MCInstrDesc &MCID = MI->getDesc();
306 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
307 MCID.OpInfo[IIOpNum].isOptionalDef();
317 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
[all...] |
| ScheduleDAGFast.cpp | 252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
253 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
259 if (MCID.isCommutable())
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
427 unsigned NumRes = MCID.getNumDefs();
428 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
503 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
504 if (!MCID.ImplicitDefs
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 96 namespace MCID {
190 return Flags & (1 << MCID::Variadic);
196 return Flags & (1 << MCID::HasOptionalDef);
203 return Flags & (1 << MCID::Pseudo);
207 return Flags & (1 << MCID::Return);
211 return Flags & (1 << MCID::Call);
218 return Flags & (1 << MCID::Barrier);
228 return Flags & (1 << MCID::Terminator);
236 return Flags & (1 << MCID::Branch);
242 return Flags & (1 << MCID::IndirectBranch)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | [all...] |
