| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
73 MIB.addReg(DestReg, RegState::Define);
76 MIB.addReg(ZeroReg);
79 MIB.addReg(SrcReg, getKillRegState(KillSrc));
|
| MipsInstrInfo.cpp | 68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
70 return &*MIB;
178 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
181 MIB.addReg(Cond[i].getReg());
183 MIB.addMBB(TBB);
|
| MipsLongBranch.cpp | 223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
233 MIB.addReg(MO.getReg());
236 MIB.addMBB(MBBOpnd);
|
| MipsSEInstrInfo.cpp | 142 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
145 MIB.addReg(DestReg, RegState::Define);
148 MIB.addReg(ZeroReg);
151 MIB.addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
123 return &*MIB;
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(),
190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 280 MachineInstrBuilder MIB =
283 AddDefaultPred(MIB);
284 MIB->copyImplicitOps(&*MBBI);
304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
305 AddDefaultPred(MIB);
323 MIB.addReg(Reg, getKillRegState(isKill));
325 MIB.setMIFlags(MachineInstr::FrameSetup);
343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
344 AddDefaultPred(MIB);
354 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB =
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
263 MIB = AddDefaultT1CC(MIB)
[all...] |
| MLxExpansionPass.cpp | 227 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
231 MIB.addImm(LaneImm);
232 MIB.addImm(Pred).addReg(PredReg);
234 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
239 MIB.addReg(TmpReg, getKillRegState(true))
242 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
244 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
|
| ARMBaseRegisterInfo.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMFrameLowering.cpp | 222 MachineInstrBuilder MIB =
226 AddDefaultCC(AddDefaultPred(MIB));
445 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
447 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
451 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
456 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
626 MachineInstrBuilder MIB =
630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
632 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
637 AddDefaultPred(MIB);
[all...] |
| Thumb2SizeReduction.cpp | 456 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
458 MIB.addOperand(MI->getOperand(0));
459 MIB.addOperand(MI->getOperand(1));
462 MIB.addImm(OffsetImm / Scale);
467 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
472 MIB.addOperand(MI->getOperand(OpNum));
475 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
478 MIB.setMIFlags(MI->getFlags());
480 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
517 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| ARMBaseInstrInfo.cpp | 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
679 AddDefaultPred(MIB);
743 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
747 return MIB.addReg(Reg, State);
750 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
751 return MIB.addReg(Reg, State, SubIdx);
818 MachineInstrBuilder MIB =
822 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI)
[all...] |
| ARMFastISel.cpp | 221 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
223 const MachineInstrBuilder &MIB,
269 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
270 MachineInstr *MI = &*MIB;
276 AddDefaultPred(MIB);
283 AddDefaultT1CC(MIB);
285 AddDefaultCC(MIB);
287 return MIB;
661 MachineInstrBuilder MIB;
664 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg
[all...] |
| ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 356 MachineInstrBuilder MIB;
364 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
370 MIB = BuildMI(&MBB, DL, get(SPU::BR));
371 MIB.addMBB(TBB);
374 DEBUG((*MIB).dump());
378 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
379 MIB.addSym(branchLabel);
380 MIB.addMBB(TBB);
384 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
385 MIB.addReg(Cond[1].getReg()).addMBB(TBB)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
395 return &*MIB;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin();
62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
99 MachineBasicBlock::iterator MIB = MBB->begin();
121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 752 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
753 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
754 return &*MIB;
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
