| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 77 unsigned NumRegs = RC->getNumRegs();
80 RCI.Order.reset(new unsigned[NumRegs]);
99 RCI.NumRegs = N + CSRAlias.size();
100 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
106 if (StressRA && RCI.NumRegs > StressRA)
107 RCI.NumRegs = StressRA;
111 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
116 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| VirtRegMap.cpp | 66 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
67 Virt2PhysMap.resize(NumRegs);
68 Virt2StackSlotMap.resize(NumRegs);
69 Virt2SplitMap.resize(NumRegs);
|
| ExecutionDepsFix.cpp | 134 const unsigned NumRegs;
149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
251 assert(unsigned(rx) < NumRegs && "Invalid index");
263 assert(unsigned(rx) < NumRegs && "Invalid index");
274 assert(unsigned(rx) < NumRegs && "Invalid index");
306 for (unsigned rx = 0; rx != NumRegs; ++rx)
330 for (unsigned rx = 0; rx != NumRegs; ++rx)
346 LiveRegs = new LiveReg[NumRegs];
349 for (unsigned rx = 0; rx != NumRegs; ++rx) {
380 for (unsigned rx = 0; rx != NumRegs; ++rx)
[all...] |
| LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
508 unsigned NumRegs = TRI->getNumRegs();
509 PhysRegDef = new MachineInstr*[NumRegs];
510 PhysRegUse = new MachineInstr*[NumRegs];
512 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
513 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
666 for (unsigned i = 0; i != NumRegs; ++i)
670 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
671 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0)
[all...] |
| MachineLICM.cpp | 496 unsigned NumRegs = TRI->getNumRegs();
497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
533 BitVector TermRegs(NumRegs);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 30 unsigned NumRegs;
34 RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
36 return makeArrayRef(Order.get(), NumRegs);
81 return get(RC).NumRegs;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 346 bool NumRegs = false;
359 NumRegs = true;
363 if (NumRegs)
|
| ARMBaseRegisterInfo.cpp | 147 unsigned NumRegs = SubIndices.size();
148 if (NumRegs == 8) {
159 } else if (NumRegs == 4) {
196 } else if (NumRegs == 2) {
[all...] |
| ARMExpandPseudoInsts.cpp | 107 unsigned char NumRegs; // D registers loaded or stored
381 unsigned NumRegs = TableEntry->NumRegs;
392 if (NumRegs > 1 && TableEntry->copyAllListRegs)
394 if (NumRegs > 2 && TableEntry->copyAllListRegs)
396 if (NumRegs > 3 && TableEntry->copyAllListRegs)
446 unsigned NumRegs = TableEntry->NumRegs;
467 if (NumRegs > 1 && TableEntry->copyAllListRegs)
469 if (NumRegs > 2 && TableEntry->copyAllListRegs
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 290 unsigned NumRegs = Regs.size();
291 if (NumRegs <= 1)
300 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA)
302 else if (Offset == -4 * (int)NumRegs && isNotVFP)
313 if (NumRegs <= 2)
320 NewBase = Regs[NumRegs-1].first;
352 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 231 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
232 for (unsigned i = 0; i != NumRegs; ++i) {
|
| LegalizeDAG.cpp | 330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
344 for (unsigned i = 1; i < NumRegs; i++) {
453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
464 for (unsigned i = 1; i < NumRegs; i++) {
[all...] |
| LegalizeIntegerTypes.cpp | 699 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
700 // The argument is passed as NumRegs registers of type RegVT.
702 SmallVector<SDValue, 8> Parts(NumRegs);
703 for (unsigned i = 0; i < NumRegs; ++i) {
716 for (unsigned i = 1; i < NumRegs; ++i) {
[all...] |
| SelectionDAGBuilder.cpp | 230 unsigned NumRegs =
233 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
234 NumParts = NumRegs; // Silence a compiler warning.
507 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
512 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
513 NumParts = NumRegs; // Silence a compiler warning.
593 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
595 for (unsigned i = 0; i != NumRegs; ++i)
598 Reg += NumRegs;
664 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 149 unsigned NumRegs; // Number of entries in the array
240 NumRegs = NR;
297 assert(RegNo < NumRegs &&
333 return NumRegs;
373 assert(RegNo < NumRegs &&
|
| /external/v8/src/ |
| frames.cc | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 771 unsigned NumRegs;
780 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
790 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds
792 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds
799 return NumRegs == ~0u;
858 ++NumRegs;
[all...] |
