| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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| ssearch.cpp | 674 struct Order
676 int32_t order; member in struct:Order
689 void add(int32_t order, int32_t low, int32_t high);
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
716 int32_t order, low, high; local
732 list = new Order[listMax];
738 order = ucol_next(elems, &status);
741 if (order != UCOL_NULLORDER)
788 const Order *order = get(index); local
799 const Order *order = get(index); local
810 const Order *order = get(index); local
875 const Order *order = list.get(i); local
893 const Order *order = list.get(i); local
991 int32_t order, low, high; local
1116 uint64_t order; local
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
43 // The remaining allocation order may depend on the hint.
44 ArrayRef<uint16_t> Order =
47 if (Order.empty())
50 // Copy the allocation order with reserved registers removed.
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i])
[all...] |
| CriticalAntiDepBreaker.cpp | 381 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
382 for (unsigned i = 0; i != Order.size(); ++i) {
383 unsigned NewReg = Order[i];
520 // the anti-dependencies in an instruction in order to be effective.
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| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
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| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 32 OwningArrayPtr<unsigned> Order;
36 return makeArrayRef(Order.get(), NumRegs);
84 /// getOrder - Returns the preferred allocation order for RC. The order
122 /// Allocatable registers may show up in the allocation order of some virtual
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| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
67 /// Order - Additional information about Order dependencies.
81 } Order;
109 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
110 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
113 case Order:
115 Contents.Order.isNormalMemory = isNormalMemory;
116 Contents.Order.isMustAlias = isMustAlias;
117 Contents.Order.isArtificial = isArtificial
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 119 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
120 for (unsigned i = 0; i != Order.size(); ++i)
121 R.set(Order[i]);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
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| SelectionDAGDumper.cpp | 488 if (unsigned Order = G->GetOrdering(this))
489 OS << " [ORD=" << Order << ']';
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| SelectionDAGBuilder.cpp | [all...] |
| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/llvm/lib/MC/ |
| MachObjectWriter.cpp | 383 // when we see the attribute, but that makes getting the order in the symbol
453 // The particular order that we collect the symbols and create the string
525 // External and undefined symbols are required to be in lexicographic order.
546 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
547 for (int i = 0, n = Order.size(); i != n ; ++i) {
548 const MCSectionData *SD = Order[i];
784 // Write the section relocation entries, in reverse order to match 'as'
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| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 590 // The list of overlaps doesn't need to have any particular order, and Reg
687 ArrayRef<Record*> Order = RC.getOrder();
696 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
697 Record *Reg = Order[i];
706 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
707 Record *Reg = Order[i];
864 ArrayRef<Record*> Order = RC.getOrder();
867 AllocatableRegs.insert(Order.begin(), Order.end());
[all...] |
| CodeGenRegisters.cpp | 180 // Merge two RegUnitLists maintaining the order and removing duplicates.
231 // Here the order is important - earlier subregs take precedence.
273 // Work backwards in the Indices vector in order to compose subregs bottom-up.
483 // Also compute the TopoSigId in post-order.
708 // Allocation order 0 is the full set. AltOrders provides others.
713 // Default allocation order always contains all registers.
722 SetTheory::RecSet Order;
724 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
725 Orders[1 + i].append(Order.begin(), Order.end())
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 757 // doesn't implicitly ignore high-order bits when doing
[all...] |
| CGExpr.cpp | [all...] |
| /external/mesa3d/src/mesa/main/ |
| mtypes.h | 993 /* Fields are in the order in which they're applied... */
[all...] |
