| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 68 SmallVector<ISD::OutputArg, 4> Outs;
70 Fn->getAttributes().getRetAttributes(), Outs, TLI);
73 Outs, Fn->getContext());
|
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 293 const SmallVectorImpl<ISD::OutputArg> &Outs,
305 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
377 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
386 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
412 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
414 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
423 Outs, OutVals, Ins, DAG);
451 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 688 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
712 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 273 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
291 Outs, OutVals, Ins, dl, DAG, InVals);
385 const SmallVectorImpl<ISD::OutputArg> &Outs,
393 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
401 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
444 &Outs,
454 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 284 const SmallVectorImpl<ISD::OutputArg> &Outs,
381 if (Outs[i].Flags.isByVal() == false) {
404 unsigned align = Outs[i].Flags.getByValAlign();
446 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
463 assert((Outs.size() == Args.size()) &&
468 for (unsigned i=0, e=Outs.size(); i!=e; ++i) {
469 EVT VT = Outs[i].VT;
471 if (Outs[i].Flags.isByVal() == false) {
497 if (Outs[i].Flags.isZExt()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 82 const SmallVectorImpl<ISD::OutputArg> &Outs,
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
352 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
368 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
380 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
381 ISD::ArgFlagsTy Flags = Outs[i].Flags;
414 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 741 SmallVector<ISD::OutputArg, 4> Outs;
743 Outs, TLI);
749 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
782 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
788 if (Outs[0].Flags.isSExt())
793 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
