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    Searched defs:PhysReg (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/CodeGen/
LiveRegMatrix.cpp 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
74 << " to " << PrintReg(PhysReg, TRI) << ':');
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
77 MRI->setPhysRegUsed(PhysReg);
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
89 << " from " << PrintReg(PhysReg, TRI) << ':');
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
100 unsigned PhysReg) {
111 // The BitVector is indexed by PhysReg, not register unit
    [all...]
RegisterClassInfo.cpp 89 unsigned PhysReg = RawOrder[i];
91 if (Reserved.test(PhysReg))
93 if (CSRNum[PhysReg])
94 // PhysReg aliases a CSR, save it for later.
95 CSRAlias.push_back(PhysReg);
97 RCI.Order[N++] = PhysReg;
VirtRegMap.cpp 81 unsigned physReg = Hint.second;
82 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
83 physReg = getPhys(physReg);
85 return (TargetRegisterInfo::isPhysicalRegister(physReg))
86 ? physReg : 0;
87 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
235 // assigned PhysReg must be marked as live-in to those blocks.
236 unsigned PhysReg = VRM->getPhys(VirtReg)
    [all...]
InterferenceCache.h 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
100 PhysReg = 0;
106 unsigned getPhysReg() const { return PhysReg; }
114 /// valid - Return true if this is a valid entry for physReg
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RegAllocFast.cpp 73 unsigned PhysReg; // Currently held here.
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
221 if (MO.getReg() == LR.PhysReg)
224 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
231 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &
    [all...]
RegAllocGreedy.cpp 183 unsigned PhysReg;
188 // Interference for PhysReg.
196 PhysReg = Reg;
216 /// Candidate info for for each PhysReg in AllocationOrder.
442 unsigned PhysReg;
443 while ((PhysReg = Order.next()))
444 if (!Matrix->checkInterference(VirtReg, PhysReg))
446 if (!PhysReg || Order.isHint(PhysReg))
447 return PhysReg;
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp     [all...]

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