| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 56 unsigned Reg = *Pos++;
57 if (Reg != Hint)
58 return Reg;
|
| RegAllocBase.cpp | 71 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
72 if (MRI->reg_nodbg_empty(Reg))
74 enqueue(&LIS->getInterval(Reg));
85 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
90 LIS->removeInterval(VirtReg->reg);
101 << MRI->getRegClass(VirtReg->reg)->getName()
102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
121 VRM->assignVirt2Phys(VirtReg->reg,
[all...] |
| DeadMachineInstructionElim.cpp | 70 unsigned Reg = MO.getReg();
71 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
73 if (LivePhysRegs.test(Reg) || ReservedRegs.test(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
110 unsigned Reg = *LOI;
111 if (TargetRegisterInfo::isPhysicalRegister(Reg))
112 LivePhysRegs.set(Reg);
140 unsigned Reg = MO.getReg();
141 if (!TargetRegisterInfo::isVirtualRegister(Reg))
[all...] |
| ProcessImplicitDefs.cpp | 78 unsigned Reg = MI->getOperand(0).getReg();
80 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 MRI->use_nodbg_begin(Reg),
110 !TRI->regsOverlap(Reg, UserReg))
112 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| CalcSpillWeights.cpp | 50 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
51 if (MRI.reg_nodbg_empty(Reg))
53 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
58 // Return the preferred allocation register for reg, given a COPY instruction.
59 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
63 if (mi->getOperand(0).getReg() == reg) {
79 const TargetRegisterClass *rc = mri.getRegClass(reg);
85 // reg:sub should match the physreg hreg.
125 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
130 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
[all...] |
| LiveRangeEdit.cpp | 148 void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
149 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
150 LIS.removeInterval(Reg);
158 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
197 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
206 DefMI->addRegisterDead(LI->reg, 0);
249 unsigned Reg = MOI->getReg();
250 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
252 if (Reg && MOI->readsReg() && !LIS.isReserved(Reg))
[all...] |
| MachineCopyPropagation.cpp | 49 void SourceNoLongerAvailable(unsigned Reg,
62 MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
65 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
229 unsigned Reg = MO.getReg();
230 if (!Reg)
233 if (TargetRegisterInfo::isVirtualRegister(Reg))
238 Defs.push_back(Reg);
242 // If 'Reg' is defined by a copy, the copy is no longer a candidate
244 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
261 unsigned Reg = (*DI)->getOperand(0).getReg()
[all...] |
| MachineInstrBundle.cpp | 131 unsigned Reg = MO.getReg();
132 if (!Reg)
134 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
135 if (LocalDefSet.count(Reg)) {
139 KilledDefSet.insert(Reg);
141 if (ExternUseSet.insert(Reg)) {
142 ExternUses.push_back(Reg);
144 UndefUseSet.insert(Reg);
148 KilledUseSet.insert(Reg);
154 unsigned Reg = MO.getReg()
[all...] |
| MachineRegisterInfo.cpp | 45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 VRegInfo[Reg].first = RC;
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
90 setRegClass(Reg, NewRC);
104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
79 if (Reg == 0) {
93 if (HiRegList[i] == Reg)
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
124 if (Reg == 0
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 58 void Hexagon_CCState::MarkAllocated(unsigned Reg) {
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0;
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0;
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonCallingConvLower.h | 74 bool isAllocated(unsigned Reg) const {
75 return UsedRegs[Reg/32] & (1 << (Reg&31));
121 unsigned AllocateReg(unsigned Reg) {
122 if (isAllocated(Reg)) return 0;
123 MarkAllocated(Reg);
124 return Reg;
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
129 if (isAllocated(Reg)) return 0;
130 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 125 unsigned Reg = MO.getReg();
126 if (!Reg)
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
167 unsigned Reg = isSub
170 if (Reg) {
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL
[all...] |
| X86FloatingPoint.cpp | 1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
118 unsigned Reg = *I - X86::FP0;
119 if (Reg < 8)
120 Mask |= 1 << Reg;
227 void pushReg(unsigned Reg) {
228 assert(Reg < NumFPRegs && "Register number out of range!");
231 Stack[StackTop] = Reg;
232 RegMap[Reg] = StackTop++;
288 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
298 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] i
[all...] |
| X86InstrBuilder.h | 44 unsigned Reg;
56 Base.Reg = 0;
64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
92 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
103 /// [Reg + Offset], i.e., one with no scale or index, but with a
108 unsigned Reg, bool isKill, int Offset) {
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
113 /// [Reg + Reg]
[all...] |
| /external/qemu/target-i386/ |
| ops_sse_header.h | 21 #define Reg MMXReg
24 #define Reg XMMReg
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 43 unsigned Reg;
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 170 unsigned Reg = CSI[I].getReg();
171 if (Reg == SPU::R0) continue;
173 MachineLocation CSSrc(Reg);
|
| SPURegisterInfo.cpp | 183 report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
352 unsigned Reg = RS->FindUnusedReg(RC);
353 if (Reg == 0)
354 Reg = RS->scavengeRegister(RC, II, SPAdj);
355 assert( Reg && "Register scavenger failed");
356 return Reg;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 196 unsigned Reg = CSI[i-1].getReg();
198 MBB.addLiveIn(Reg);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 88 unsigned Reg);
215 unsigned Reg;
217 if (!MO.isReg() || !(Reg = MO.getReg()))
221 // check whether Reg is defined or used before delay slot.
222 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
226 // check whether Reg is defined before delay slot.
227 if (IsRegInSet(RegDefs, Reg))
249 unsigned Reg;
251 if (!MO.isReg() || !(Reg = MO.getReg())
[all...] |
| MipsSERegisterInfo.cpp | 128 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
129 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg);
|
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 31 if (!Reg)
33 else if (TargetRegisterInfo::isStackSlot(Reg))
34 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
35 else if (TargetRegisterInfo::isVirtualRegister(Reg))
36 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
40 OS << "%physreg" << Reg;
97 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
98 assert(isPhysicalRegister(reg) && "reg must be a physical register")
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 151 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
152 if (!LiveOutRegInfo.inBounds(Reg))
155 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
167 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
170 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
176 LiveOutRegInfo.grow(Reg);
177 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
195 unsigned Reg = It->second;
196 LiveOutRegInfo.grow(Reg);
197 LiveOutRegInfo[Reg].IsValid = false
[all...] |
