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    Searched defs:SetCC (Results 1 - 6 of 6) sorted by null

  /external/v8/src/ia32/
disasm-ia32.cc 361 int SetCC(byte* data);
658 int DisassemblerIA32::SetCC(byte* data) {
1048 data += SetCC(data);
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  /external/v8/src/x64/
disasm-x64.cc 431 int SetCC(byte* data);
825 int DisassemblerX64::SetCC(byte* data) {
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  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
494 // Promote all the way up to the canonical SetCC type.
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
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DAGCombiner.cpp 531 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
532 // that selects between the values 1 and 0, making it equivalent to a setcc.
538 if (N.getOpcode() == ISD::SETCC) {
557 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
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  /external/v8/src/arm/
constants-arm.h 273 SetCC = 1 << 20, // Set condition code.
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp 169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
449 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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