/external/v8/src/mips/ |
constants-mips.cc | 315 case ANDI:
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constants-mips.h | 267 ANDI = ((1 << 3) + 4) << kOpcodeShift,
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assembler-mips.cc | 650 return GetOpcodeField(instr) == ANDI; 1246 void Assembler::andi(Register rt, Register rs, int32_t j) { function in class:v8::Assembler [all...] |
simulator-mips.cc | [all...] |
/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.h | 305 void ANDI(int Rd, int Rs, uint16_t imm);
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MIPSAssembler.cpp | 437 mMips->ANDI(Rd, Rn, src); [all...] |
/external/qemu/tcg/ppc/ |
tcg-target.c | 321 #define ANDI OPCD(28) [all...] |
/external/qemu/tcg/ppc64/ |
tcg-target.c | 309 #define ANDI OPCD( 28) [all...] |
/external/llvm/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 52 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 262 // andi samt, samt, 31 295 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) 442 // andi samt, samt, 31 [all...] |