/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 78 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); 88 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo) [all...] |
LegalizeVectorOps.cpp | 303 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 310 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 486 // Bitcast the operands to be the same type as the mask. 489 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 490 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 499 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 528 // Bitcast the operands to be the same type as the mask. 531 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 532 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); 541 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val) [all...] |
LegalizeVectorTypes.cpp | 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 365 case ISD::BITCAST: 399 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 480 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 620 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 621 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 629 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 630 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 644 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo) [all...] |
SelectionDAGBuilder.cpp | 132 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 133 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 165 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 166 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 208 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 283 // Vector/Vector bitcast. 285 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 296 // Trivial bitcast if the types are the same size and the destination 300 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 363 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val) [all...] |
LegalizeDAG.cpp | 315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 735 Value = DAG.getNode(ISD::BITCAST, dl, [all...] |
LegalizeFloatTypes.cpp | 59 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; 584 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; 697 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), [all...] |
FastISel.cpp | 116 !(I->getOpcode() == Instruction::BitCast || 730 // If the bitcast doesn't change the type, just use the operand value. 739 // Bitcasts of other values become reg-reg copies or BITCAST operators. 756 // First, try to perform the bitcast by inserting a reg-reg copy. 769 // If the reg-reg copy failed, select a BITCAST opcode. 772 ISD::BITCAST, Op0, Op0IsKill); 870 // Bitcast the value to integer, twiddle the sign bit with xor, 871 // and then bitcast it back to floating-point. 878 ISD::BITCAST, OpReg, OpRegIsKill); 890 ISD::BITCAST, IntResultReg, /*Kill=*/true) [all...] |
DAGCombiner.cpp | [all...] |
SelectionDAGDumper.cpp | 228 case ISD::BITCAST: return "bitcast";
|
LegalizeTypes.cpp | [all...] |
LegalizeIntegerTypes.cpp | 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 254 // make us bitcast between two vectors which are legalized in different ways. 256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); 759 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; [all...] |
SelectionDAG.cpp | 115 if (N->getOpcode() == ISD::BITCAST) 165 if (N->getOpcode() == ISD::BITCAST) [all...] |
TargetLowering.cpp | [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 359 setOperationAction(ISD::BITCAST, MVT::i32, Legal); 360 setOperationAction(ISD::BITCAST, MVT::f32, Legal); 361 setOperationAction(ISD::BITCAST, MVT::i64, Legal); 362 setOperationAction(ISD::BITCAST, MVT::f64, Legal); 689 DAG.getNode(ISD::BITCAST, dl, vecVT, result)); 702 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones); 729 result = DAG.getNode(ISD::BITCAST, dl, vecVT, [all...] |
SPUISelDAGToDAG.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 423 /// BITCAST - This operator converts between integer, vector and FP 430 BITCAST, [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 335 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 336 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 338 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 340 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); [all...] |
X86FastISel.cpp | 364 case Instruction::BitCast: 612 case Instruction::BitCast: [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 207 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 215 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 262 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 434 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 524 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 732 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 733 setOperationAction(ISD::BITCAST, MVT::i32, Expand); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
ARMFastISel.cpp | 805 case Instruction::BitCast: { [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 196 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 197 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 198 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 199 setOperationAction(ISD::BITCAST, MVT::f64, Expand); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 126 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 127 setOperationAction(ISD::BITCAST, MVT::i32, Expand); [all...] |