| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 36 ARMCC::CondCodes Pred = ARMCC::AL,
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| Thumb2ITBlockPass.cpp | 43 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
105 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
153 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
193 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
206 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
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| Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
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| Thumb1RegisterInfo.h | 42 ARMCC::CondCodes Pred = ARMCC::AL,
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| ARMBaseInstrInfo.h | 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
358 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
379 ARMCC::CondCodes Pred, unsigned PredReg,
385 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
108 ARMCC::CondCodes Pred,
115 ARMCC::CondCodes Pred, unsigned PredReg,
285 int Opcode, ARMCC::CondCodes Pred,
371 ARMCC::CondCodes Pred, unsigned PredReg,
448 ARMCC::CondCodes Pred, unsigned PredReg,
531 ARMCC::CondCodes Pred, unsigned PredReg) {
564 ARMCC::CondCodes Pred, unsigned PredReg) {
719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
872 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg)
[all...] |
| ARMBaseRegisterInfo.h | 168 ARMCC::CondCodes Pred = ARMCC::AL,
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| MLxExpansionPass.cpp | 218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
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| ARMBaseInstrInfo.cpp | 157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
[all...] |
| Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
180 ARMCC::CondCodes Pred, unsigned PredReg,
566 ARMCC::CondCodes
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| ARMBaseRegisterInfo.cpp | 709 ARMCC::CondCodes Pred,
749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
785 ARMCC::CondCodes Pred = (PIdx == -1)
786 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
[all...] |
| Thumb2SizeReduction.cpp | 154 bool is2Addr, ARMCC::CondCodes Pred,
254 bool is2Addr, ARMCC::CondCodes Pred,
644 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
736 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelLowering.h | 530 ARMCC::CondCodes Cond) const;
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| ARMISelDAGToDAG.cpp | 243 ARMCC::CondCodes CCVal, SDValue CCR,
246 ARMCC::CondCodes CCVal, SDValue CCR,
249 ARMCC::CondCodes CCVal, SDValue CCR,
252 ARMCC::CondCodes CCVal, SDValue CCR,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430.h | 23 enum CondCodes {
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| MSP430InstrInfo.cpp | 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
225 MSP430CC::CondCodes BranchCode =
226 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTX.h | 32 enum CondCodes {
42 inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
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| /external/llvm/lib/Target/Sparc/ |
| Sparc.h | 37 enum CondCodes {
74 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
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| SparcInstrInfo.cpp | 79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
181 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
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| SparcAsmPrinter.cpp | 177 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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| SparcISelLowering.cpp | 649 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
667 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 27 // The CondCodes constants map directly to the 4-bit encoding of the
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
47 inline static CondCodes getOppositeCondition(CondCodes CC) {
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 746 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
757 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
[all...] |
