| /external/clang/test/CodeGen/ |
| mips64-class-return.cpp | 7 class D0 : public B0 {
23 extern D0 gd0;
28 D0 foo1(void) {
43 void foo4(D0 a0) {
|
| /frameworks/av/media/libeffects/lvm/lib/SpectrumAnalyzer/src/ |
| LVPSA_QPD_Process.c | 77 LVM_INT16 D0;
114 D0 = (LVM_INT16)(Xg0 - V0);
116 temp2 = (LVM_INT32)D0;
119 D0 = (LVM_INT16)(D0>>1);
120 if (D0 < 0){
121 D0 = (LVM_INT16)(-D0);
124 temp2 = (LVM_INT32)D0;
125 MUL32x32INTO32((LVM_INT32)D0,Km,temp,31)
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| syn_filt_neon.s | 45 VLD1.S16 {D0, D1, D2, D3}, [r4]! @load 16 mems
46 VST1.S16 {D0, D1, D2, D3}, [r5]! @store 16 mem[] to *yy
53 VLD1.S16 {D0, D1, D2, D3}, [r0]! @ load a[1] ~ a[16]
54 VREV64.16 D0, D0
74 VMLAL.S16 Q5, D0, D7
96 VLD1.S16 {D0, D1, D2, D3}, [r5]!
97 VST1.S16 {D0, D1, D2, D3}, [r3]!
|
| convolve_neon.s | 54 VLD1.S16 D0, [r6]!
58 VMLAL.S16 Q10, D0, D1
90 VLD1.S16 D0, [r6]!
94 VMLAL.S16 Q10, D0, D1
128 VLD1.S16 D0, [r6]!
132 VMLAL.S16 Q10, D0, D1
154 VLD1.S16 D0, [r6]!
158 VMLAL.S16 Q10, D0, D1
|
| Dot_p_neon.s | 47 VMULL.S16 Q15, D16, D0
60 VMLAL.S16 Q15, D0, D12
69 VMLAL.S16 Q15, D4, D0
80 VMULL.S16 Q15, D0, D0
100 VMLAL.S16 Q15, D0, D0
|
| Filt_6k_7k_neon.s | 42 VLD1.S16 {D0, D1, D2, D3}, [r0]!
45 VST1.S16 {D0, D1, D2, D3}, [r1]!
101 VMULL.S16 Q9,D8,D0[0]
103 VMULL.S16 Q11,D9,D0[0]
122 VMLAL.S16 Q9,D8,D0[1]
125 VMLAL.S16 Q11,D9,D0[1]
144 VMLAL.S16 Q9,D8,D0[2]
147 VMLAL.S16 Q11,D9,D0[2]
166 VMLAL.S16 Q9,D8,D0[3]
169 VMLAL.S16 Q11,D9,D0[3
[all...] |
| Syn_filt_32_neon.s | 52 VLD1.S16 {D0, D1, D2, D3}, [r0]! @a[1] ~ a[16]
57 VREV64.16 D0, D0
72 VMLAL.S16 Q10, D11, D0
89 VMLAL.S16 Q11, D7, D0
|
| residu_asm_neon.s | 36 VLD1.S16 {D0, D1, D2, D3}, [r0]! @get all a[]
45 VQDMULL.S16 Q10, D5, D0[0] @finish the first L_mult
49 VQDMLAL.S16 Q10, D5, D0[1]
53 VQDMLAL.S16 Q10, D5, D0[2]
57 VQDMLAL.S16 Q10, D5, D0[3]
|
| Norm_Corr_neon.s | 78 VMULL.S16 Q10, D0, D0
120 VMULL.S16 Q10, D0, D0 @L_tmp1 += excf[] * excf[]
121 VMULL.S16 Q11, D0, D8 @L_tmp += x[] * excf[]
141 VMLAL.S16 Q10, D0, D0
142 VMLAL.S16 Q11, D0, D8
|
| scale_sig_neon.s | 52 VSHLL.S16 Q10, D0, #16
72 VSHLL.S16 Q8, D0, #16
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.s | 124 dSrcRow0 DN D0.I16
128 dDqntRow0 DN D0.I16
136 dIn0 DN D0.S16
151 df0 DN D0.S16
165 dh0 DN D0.S16
172 dDeltaRow0 DN D0.S16
184 dDstRow01 DN D0.U8
186 dDstRow0 DN D0.32[0]
187 dDstRow1 DN D0.32[1]
294 VADD de0,dIn0,dIn2 ;// e0 = d0 + d2
[all...] |
| armVCM4P10_TransformResidual4x4_s.s | 59 dIn0 DN D0.S16
72 df0 DN D0.S16
86 dh0 DN D0.S16
120 VADD de0,dIn0,dIn2 ;// e0 = d0 + d2
121 VSUB de1,dIn0,dIn2 ;// e1 = d0 - d2
147 VADD dg0,df0,df2 ;// e0 = d0 + d2
148 VSUB dg1,df0,df2 ;// e1 = d0 - d2
|
| omxVCM4P10_TransformDequantChromaDCFromPair_s.s | 64 dZero DN D0.U16
65 dInvTrCoeff DN D0.S16
|
| omxVCM4P10_TransformDequantLumaDCFromPair_s.s | 65 dIn0 DN D0.S16
77 dRowOp0 DN D0.S16
91 dColOp0 DN D0.S16
105 dOut0 DN D0.S16
|
| omxVCM4P10_PredictIntra_4x4_s.s | 68 dAboveU32 DN D0.U32
71 dLeftVal0 DN D0.8
75 dLeftVal0U32 DN D0.U32
81 dLeftVal DN D0.U8
82 dLeftValU32 DN D0.U32
87 dSum DN D0.U8
94 dAboveVal DN D0.U8
99 dConst128U8 DN D0.U8
104 dAbove DN D0.U8
|
| armVCM4P10_Interpolate_Chroma_s.s | 67 dRow0a DN D0.U8
106 dOut0U64 DN D0.U64
109 dOut00U32 DN D0.U32
114 dOut0U16 DN D0.U16
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| armVCM4P2_Clip8_s.s | 32 dx00 DN D0.S16
46 dclip0 DN D0.U8
|
| omxVCM4P2_QuantInvInter_I_s.s | 73 dQP10 DN D0.S32[0]
76 dQP1 DN D0.S16
|
| /external/llvm/test/MC/MachO/ |
| x86_32-symbols.s | 5 D0:
701 // CHECK: ('_string', 'D0')
|
| x86_64-symbols.s | 5 D0:
658 // CHECK: ('_string', 'D0')
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/comm/src/ |
| omxVCCOMM_Copy8x8_s.s | 37 X0 DN D0.S8
|
| omxVCCOMM_Copy16x16_s.s | 36 X0 DN D0.S8
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 66 Hexagon::D0, Hexagon::D1, Hexagon::D2
122 Hexagon::D0, Hexagon::D1, Hexagon::D2
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 351 const TargetRegisterInfo *TRI, unsigned &D0,
354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
389 unsigned D0, D1, D2, D3;
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
464 unsigned D0, D1, D2, D3;
465 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
466 MIB.addReg(D0, getUndefRegState(SrcIsUndef))
[all...] |
| /external/speex/libspeex/ |
| math_approx.h | 245 #define D0 16384
260 frac = ADD16(D0, MULT16_16_Q14(frac, ADD16(D1, MULT16_16_Q14(frac, ADD16(D2 , MULT16_16_Q14(D3,frac))))));
|
