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    Searched refs:DefReg (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/CodeGen/
TargetInstrInfoImpl.cpp 387 unsigned DefReg = MI->getOperand(0).getReg();
393 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
394 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
445 if (MO.isDef() && Reg != DefReg)
TailDuplication.cpp 392 unsigned DefReg = MI->getOperand(0).getReg();
396 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
397 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
403 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
404 AddSSAUpdateEntry(DefReg, NewDef, PredBB);
    [all...]
PHIElimination.cpp 139 unsigned DefReg = DefMI->getOperand(0).getReg();
140 if (MRI->use_nodbg_empty(DefReg))
LiveVariables.cpp 218 unsigned DefReg = MO.getReg();
219 if (TRI->isSubRegister(Reg, DefReg)) {
220 PartDefRegs.insert(DefReg);
221 for (MCSubRegIterator SubRegs(DefReg, TRI); SubRegs.isValid(); ++SubRegs)
TwoAddressInstructionPass.cpp 199 unsigned DefReg = 0;
216 if (DefReg)
219 DefReg = MO.getReg();
267 if (DefReg == MOReg)
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 281 unsigned DefReg = MPhi->getOperand(0).getReg();
288 if (isInductionOperation(DI, DefReg)) {
  /external/llvm/lib/Target/PowerPC/
PPCCTRLoops.cpp 261 unsigned DefReg = MPhi->getOperand(0).getReg();
268 if (isInductionOperation(DI, DefReg)) {
  /external/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 406 unsigned DefReg = MO->getReg();
407 if (std::find(ImpDefs.begin(), ImpDefs.end(), DefReg) == ImpDefs.end())
408 ImpDefs.push_back(DefReg);
    [all...]

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