| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 246 EVT DstVT = Dst.getValueType();
250 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
251 DAG.getConstant(Offset, DstVT)),
|
| X86FastISel.cpp | 88 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
322 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
324 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
327 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
776 EVT DstVT = VA.getValVT();
778 if (SrcVT != DstVT) {
785 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
795 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
[all...] |
| X86ISelDAGToDAG.cpp | 480 EVT DstVT = N->getValueType(0);
483 if (SrcVT.isVector() || DstVT.isVector())
489 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
507 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
509 MemVT = SrcIsSSE ? SrcVT : DstVT;
519 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 696 EVT DstVT = TLI.getValueType(I->getType());
699 DstVT == MVT::Other || !DstVT.isSimple())
704 if (!TLI.isTypeLegal(DstVT))
719 DstVT.getSimpleVT(),
741 EVT DstVT = TLI.getValueType(I->getType());
744 DstVT == MVT::Other || !DstVT.isSimple() ||
745 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
758 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT())
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 450 EVT DstVT = TLI.getValueType(CI->getType());
453 if (SrcVT.isInteger() != DstVT.isInteger())
458 if (SrcVT.bitsLT(DstVT)) return false;
466 if (TLI.getTypeAction(CI->getContext(), DstVT) ==
468 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);
471 if (SrcVT != DstVT)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
