| /external/llvm/lib/CodeGen/ |
| TargetFrameLoweringImpl.cpp | 37 int FI, unsigned &FrameReg) const {
43 FrameReg = RI->getFrameRegister(MF);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 78 unsigned FrameReg;
82 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
84 FrameReg = getFrameRegister(MF);
106 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
|
| MipsSERegisterInfo.cpp | 92 unsigned FrameReg;
96 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
98 FrameReg = getFrameRegister(MF);
129 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg);
131 FrameReg = ATReg;
135 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.h | 53 unsigned &FrameReg) const;
56 unsigned &FrameReg, int SPAdj) const;
|
| Thumb1RegisterInfo.cpp | 388 unsigned FrameReg, int &Offset,
403 if (FrameReg != ARM::SP) {
417 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
432 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
435 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
447 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
461 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
463 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
478 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
487 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5
[all...] |
| Thumb1RegisterInfo.h | 55 unsigned FrameReg, int &Offset,
|
| Thumb2InstrInfo.cpp | 389 unsigned FrameReg, int &Offset,
407 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
428 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
441 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
477 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
532 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
| ARMFrameLowering.cpp | 482 unsigned &FrameReg) const {
483 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
488 int FI, unsigned &FrameReg,
498 FrameReg = ARM::SP;
516 FrameReg = RegInfo->getFrameRegister(MF);
521 FrameReg = RegInfo->getBaseRegister();
531 FrameReg = RegInfo->getFrameRegister(MF);
540 FrameReg = RegInfo->getFrameRegister(MF);
553 FrameReg = RegInfo->getFrameRegister(MF);
558 FrameReg = RegInfo->getFrameRegister(MF)
[all...] |
| ARMBaseRegisterInfo.cpp | [all...] |
| ARMBaseInstrInfo.h | 400 unsigned FrameReg, int &Offset,
404 unsigned FrameReg, int &Offset,
|
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 189 unsigned FrameReg = getFrameRegister(MF);
193 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
230 .addReg(FrameReg)
236 .addReg(FrameReg)
241 .addReg(FrameReg)
251 .addReg(FrameReg)
257 .addReg(FrameReg)
262 .addReg(FrameReg)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 157 unsigned FrameReg = getFrameRegister(MF);
201 dstReg).addReg(FrameReg).addReg(dstReg);
205 dstReg).addReg(FrameReg).addImm(Offset);
230 resReg).addReg(FrameReg).addReg(resReg);
234 resReg).addReg(FrameReg).addImm(Offset);
250 resReg).addReg(FrameReg).addReg(resReg);
256 resReg).addReg(FrameReg).addImm(Offset);
266 dstReg).addReg(FrameReg).addReg(dstReg);
274 MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 170 /// returned directly, and the base register is returned via FrameReg.
172 unsigned &FrameReg) const;
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 64 unsigned &FrameReg) const;
|
| X86FrameLowering.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfCompileUnit.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
