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Searched
refs:INSERT_SUBREG
(Results
1 - 8
of
8
) sorted by null
/external/llvm/include/llvm/Target/
TargetOpcodes.h
43
///
INSERT_SUBREG
- This instruction takes three operands: a register that
49
INSERT_SUBREG
= 7,
54
/// SUBREG_TO_REG - This instruction is similar to
INSERT_SUBREG
except that
/external/llvm/include/llvm/CodeGen/
MachineInstr.h
616
return getOpcode() == TargetOpcode::
INSERT_SUBREG
;
656
case TargetOpcode::
INSERT_SUBREG
:
[
all
...]
/external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp
107
assert(SubIdx != 0 && "Invalid index for
insert_subreg
");
226
case TargetOpcode::
INSERT_SUBREG
:
/external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp
265
case TargetOpcode::
INSERT_SUBREG
:
305
case TargetOpcode::
INSERT_SUBREG
:
ScheduleDAGRRList.cpp
[
all
...]
InstrEmitter.cpp
515
} else if (Opc == TargetOpcode::
INSERT_SUBREG
||
525
// the
INSERT_SUBREG
instruction.
527
// %dst =
INSERT_SUBREG
%src, %sub, SubIdx
538
assert(SRC && "No register class supports VT and SubIdx for
INSERT_SUBREG
");
543
// Create the
insert_subreg
or subreg_to_reg machine instruction.
561
llvm_unreachable("Node is not
insert_subreg
, extract_subreg, or subreg_to_reg");
700
Opc == TargetOpcode::
INSERT_SUBREG
||
[
all
...]
SelectionDAG.cpp
[
all
...]
/external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp
236
case TargetOpcode::
INSERT_SUBREG
:
281
case TargetOpcode::
INSERT_SUBREG
:
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