/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 36 if (getOpcode() < ISD::BUILTIN_OP_END) 54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; 56 case ISD::PREFETCH: return "Prefetch"; 57 case ISD::MEMBARRIER: return "MemBarrier"; 58 case ISD::ATOMIC_FENCE: return "AtomicFence"; 59 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 60 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 61 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 62 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 63 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd" [all...] |
LegalizeDAG.cpp | 270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 300 assert(ST->getAddressingMode() == ISD::UNINDEXED && 315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr [all...] |
LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 133 if (Op.getOpcode() == ISD::LOAD) { 135 ISD::LoadExtType ExtType = LD->getExtensionType(); 136 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 142 } else if (Op.getOpcode() == ISD::STORE) { 172 case ISD::ADD: 173 case ISD::SUB [all...] |
LegalizeIntegerTypes.cpp | 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 57 case ISD::CONVERT_RNDSAT: 59 case ISD::CTLZ_ZERO_UNDEF: 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break [all...] |
LegalizeVectorTypes.cpp | 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break [all...] |
TargetLowering.cpp | 495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::UNE_F32] = ISD::SETNE; 500 CCs[RTLIB::UNE_F64] = ISD::SETNE; 501 CCs[RTLIB::OGE_F32] = ISD::SETGE; 502 CCs[RTLIB::OGE_F64] = ISD::SETGE; 503 CCs[RTLIB::OLT_F32] = ISD::SETLT [all...] |
SelectionDAG.cpp | 108 // ISD Namespace 113 bool ISD::isBuildVectorAllOnes(const SDNode *N) { 115 if (N->getOpcode() == ISD::BITCAST) 118 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 123 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 155 N->getOperand(i).getOpcode() != ISD::UNDEF) 163 bool ISD::isBuildVectorAllZeros(const SDNode *N) { 165 if (N->getOpcode() == ISD::BITCAST) 168 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 173 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF [all...] |
DAGCombiner.cpp | 158 ISD::NodeType ExtType); 255 SDValue N3, ISD::CondCode CC, 257 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 393 if (Op.getOpcode() == ISD::FNEG) return 2; 403 case ISD::ConstantFP: 407 case ISD::FADD: 413 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 423 case ISD::FSUB: 430 case ISD::FMUL: 431 case ISD::FDIV [all...] |
LegalizeFloatTypes.cpp | 58 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; 59 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; 60 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; 61 case ISD::ConstantFP: 64 case ISD::EXTRACT_VECTOR_ELT: 66 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; 67 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; 68 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; 69 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; 70 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 114 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 115 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 116 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 118 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 119 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 129 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 130 setOperationAction(ISD::ConstantFP, MVT::f64, Custom); 137 setOperationAction(ISD::LOAD, VT, Custom); 138 setOperationAction(ISD::STORE, VT, Custom); 139 setLoadExtAction(ISD::EXTLOAD, VT, Custom) [all...] |
/external/llvm/lib/CodeGen/ |
Analysis.cpp | 148 /// getFCmpCondCode - Return the ISD condition code corresponding to 152 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 154 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; 155 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; 156 case FCmpInst::FCMP_OGT: return ISD::SETOGT; 157 case FCmpInst::FCMP_OGE: return ISD::SETOGE; 158 case FCmpInst::FCMP_OLT: return ISD::SETOLT; 159 case FCmpInst::FCMP_OLE: return ISD::SETOLE; 160 case FCmpInst::FCMP_ONE: return ISD::SETONE; 161 case FCmpInst::FCMP_ORD: return ISD::SETO [all...] |
/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 38 ISD::ArgFlagsTy &ArgFlags, CCState &State) 51 ISD::ArgFlagsTy &ArgFlags, CCState &State) 82 const SmallVectorImpl<ISD::OutputArg> &Outs, 150 const SmallVectorImpl<ISD::InputArg> 206 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 207 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 215 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 217 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 219 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 261 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 54 ISD::ArgFlagsTy ArgFlags, CCState &State); 59 ISD::ArgFlagsTy ArgFlags, CCState &State); 64 ISD::ArgFlagsTy ArgFlags, CCState &State); 69 ISD::ArgFlagsTy ArgFlags, CCState &State); 74 ISD::ArgFlagsTy ArgFlags, CCState &State); 79 ISD::ArgFlagsTy ArgFlags, CCState &State); 84 ISD::ArgFlagsTy ArgFlags, CCState &State) { 123 ISD::ArgFlagsTy ArgFlags, CCState &State) { 161 ISD::ArgFlagsTy ArgFlags, CCState &State) { 179 ISD::ArgFlagsTy ArgFlags, CCState &State) [all...] |
HexagonCallingConvLower.h | 38 ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State, 78 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node, 80 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 83 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node, 85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 88 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info 90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 97 SmallVectorImpl<ISD::ArgFlagsTy> &Flags, 100 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node, 102 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); 115 N.getOpcode() == ISD::TargetGlobalAddress) { 128 N.getOpcode() == ISD::TargetGlobalAddress) 276 if (N->getOpcode() != ISD::Constant) 294 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 362 if (Opcode == ISD::SHL) { 367 } else if (Opcode == ISD::SRL) { 374 } else if (Opcode == ISD::ROTL) { 412 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) [all...] |
PPCISelLowering.cpp | 41 ISD::ArgFlagsTy &ArgFlags, 46 ISD::ArgFlagsTy &ArgFlags, 51 ISD::ArgFlagsTy &ArgFlags, 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal) [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 76 if (Vec.getOpcode() == ISD::UNDEF) 89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 104 if (Vec.getOpcode() == ISD::UNDEF) 122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand) [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD::SRL, MVT::i8, Custom) [all...] |
/external/llvm/include/llvm/CodeGen/ |
SelectionDAGNodes.h | 62 namespace ISD { 74 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 79 /// and all operands of the specified node are ISD::UNDEF. 81 } // end llvm:ISD namespace 361 /// are the opcode values in the ISD and <target>ISD namespaces. For 366 /// \<target\>ISD namespace). 367 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } 370 /// memory-referencing opcode (in the \<target\>ISD namespace and 373 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE [all...] |
Analysis.h | 68 /// getFCmpCondCode - Return the ISD condition code corresponding to 72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred); 74 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, 76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC); 78 /// getICmpCondCode - Return the ISD condition code corresponding to 81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 40 ISD::ArgFlagsTy &ArgFlags, 68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 72 setOperationAction(ISD::FREM, MVT::f32, Expand); 73 setOperationAction(ISD::FMA, MVT::f32, Expand); 74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); 75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); 76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); 79 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 86 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 88 setOperationAction(ISD::ADDC, MVT::i32, Expand); 89 setOperationAction(ISD::ADDE, MVT::i32, Expand); 90 setOperationAction(ISD::SUBC, MVT::i32, Expand); 91 setOperationAction(ISD::SUBE, MVT::i32, Expand); 94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 97 setOperationAction(ISD::ADD, MVT::i64, Custom); 98 setOperationAction(ISD::SUB, MVT::i64, Custom); 99 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 137 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 148 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 150 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 102 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32 , Custom); 103 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32 , Custom); 104 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16 , Custom); 105 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8 , Custom); 106 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64 , Custom); 107 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64 , Custom); 108 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32 , Custom); 109 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32 , Custom); 110 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16 , Custom); 111 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i8 , Custom) [all...] |