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Searched
refs:ImplicitDefs
(Results
1 - 11
of
11
) sorted by null
/external/llvm/include/llvm/MC/
MCInstrDesc.h
144
const uint16_t *
ImplicitDefs
; // Registers implicitly defined by this instr
482
return
ImplicitDefs
;
488
if (
ImplicitDefs
== 0) return 0;
490
for (;
ImplicitDefs
[i]; ++i) /*empty*/;
506
if (const uint16_t *ImpDefs =
ImplicitDefs
)
/external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp
[
all
...]
ScheduleDAGFast.cpp
426
assert(MCID.
ImplicitDefs
&& "Physical reg def must be in implicit def list!");
504
if (!MCID.
ImplicitDefs
)
ScheduleDAGSDNodes.cpp
125
II.
ImplicitDefs
[ResNo - II.getNumDefs()] == Reg) {
[
all
...]
ScheduleDAGRRList.cpp
[
all
...]
/external/llvm/utils/TableGen/
CodeGenInstruction.cpp
327
ImplicitDefs
= R->getValueAsListOfDefs("Defs");
345
if (
ImplicitDefs
.empty()) return MVT::Other;
348
Record *FirstImplicitDef =
ImplicitDefs
[0];
CodeGenInstruction.h
214
///
ImplicitDefs
/ImplicitUses - These are lists of registers that are
216
std::vector<Record*>
ImplicitDefs
, ImplicitUses;
DAGISelMatcherGen.cpp
788
HandledReg = II.
ImplicitDefs
[0];
[
all
...]
CodeGenDAGPatterns.cpp
[
all
...]
/external/llvm/lib/Target/ARM/
ARMFastISel.cpp
313
.addReg(II.
ImplicitDefs
[0]));
335
.addReg(II.
ImplicitDefs
[0]));
360
.addReg(II.
ImplicitDefs
[0]));
382
.addReg(II.
ImplicitDefs
[0]));
404
.addReg(II.
ImplicitDefs
[0]));
429
.addReg(II.
ImplicitDefs
[0]));
448
.addReg(II.
ImplicitDefs
[0]));
468
.addReg(II.
ImplicitDefs
[0]));
[
all
...]
/external/llvm/lib/CodeGen/
MachineInstr.cpp
530
if (MCID->
ImplicitDefs
)
[
all
...]
Completed in 186 milliseconds