HomeSort by relevance Sort by last modified time
    Searched refs:Lane (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 89 // For quad-register load-lane and store-lane pseudo instructors, the
91 // OddDblSpc depending on the lane number operand.
108 unsigned char RegElts; // elements per D register; used for lane ops
503 // The lane operand is always the 3rd from last operand, before the 2
505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
507 // Adjust the lane and spacing as needed for Q registers.
508 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
509 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
511 Lane -= RegElts
    [all...]
ARMBaseInstrInfo.cpp 58 bool HasLane; // True if instruction has an extra "lane" operand.
    [all...]
ARMCodeEmitter.cpp     [all...]
ARMISelLowering.cpp     [all...]
ARMISelDAGToDAG.cpp 219 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
    [all...]
  /external/jpeg/
jmemdosa.asm 4 ; Copyright (C) 1992, Thomas G. Lane.
  /external/qemu/distrib/jpeg-6b/
jmemdosa.asm 4 ; Copyright (C) 1992, Thomas G. Lane.
  /external/clang/lib/CodeGen/
CGBuiltin.cpp     [all...]

Completed in 255 milliseconds