| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeAsmBackend.cpp | 73 case MBlaze::ORI: return MBlaze::ORI32;
|
| /external/v8/src/mips/ |
| constants-mips.cc | 316 case ORI:
|
| assembler-mips-inl.h | 129 // For an instruction like LUI/ORI where the target bits are mixed into the
279 (instr1 & kOpcodeMask) == ORI &&
|
| assembler-mips.cc | 182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
574 return opcode == ORI;
1257 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 268 ORI = ((1 << 3) + 5) << kOpcodeShift,
|
| simulator-mips.cc | [all...] |
| macro-assembler-mips.cc | 666 ori(rd, rs, rt.imm32_);
781 ori(rd, zero_reg, j.imm32_);
786 ori(rd, rd, (j.imm32_ & kImm16Mask));
795 ori(rd, rd, (j.imm32_ & kImm16Mask));
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 387 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
471 mMips->ORI(Rd, Rn, src);
478 mMips->ORI(R_at, 0, src);
488 mMips->ORI(R_at, 0, src);
501 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
504 mMips->ORI(Rd, 0, amode.value);
533 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
536 mMips->ORI(Rd, 0, amode.value);
579 mMips->ORI(R_cmp2, R_zero, src);
[all...] |
| MIPSAssembler.h | 307 void ORI(int Rt, int Rs, uint16_t imm);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 97 // transform this into the appropriate ORI instruction.
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
383 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
594 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
672 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
[all...] |
| PPCCTRLoops.cpp | 373 // Here we need to look for an immediate load (an li or lis/ori pair).
375 DefInstr->getOpcode() == PPC::ORI)) {
665 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
|
| PPCRegisterInfo.cpp | 234 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
600 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
|
| PPCISelLowering.cpp | [all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 305 #define ORI OPCD( 24)
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 317 #define ORI OPCD(24)
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
[all...] |
| /external/icu4c/common/ |
| ucnvisci.c | 94 ORI = 0x47,
147 { ORIYA, ORI_MASK, ORI },
270 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
[all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 52 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
