| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 102 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
103 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
104 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
105 if (unsigned N = CSRNum[PhysReg])
110 /// isReserved - Returns true when PhysReg is a reserved register.
115 bool isReserved(unsigned PhysReg) const {
116 return Reserved.test(PhysReg);
119 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
125 bool isAllocatable(unsigned PhysReg) const {
126 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg)
[all...] |
| MachineOperand.h | 454 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
458 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
460 assert(PhysReg < (1u << 30) && "Not a physical register");
461 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
464 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
465 bool clobbersPhysReg(unsigned PhysReg) const {
466 return clobbersPhysReg(getRegMask(), PhysReg);
645 /// mask has a bit set for each physreg that is preserved by this
649 /// Any physreg with a 0 bit in the mask is clobbered by the instruction
[all...] |
| MachineRegisterInfo.h | 284 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
286 /// a physreg.
287 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
333 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
423 /// canReserveReg - Returns true if PhysReg can be used as a reserved
426 bool canReserveReg(unsigned PhysReg) const {
427 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
|
| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
74 << " to " << PrintReg(PhysReg, TRI) << ':');
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
77 MRI->setPhysRegUsed(PhysReg);
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
89 << " from " << PrintReg(PhysReg, TRI) << ':');
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
100 unsigned PhysReg) {
111 // The BitVector is indexed by PhysReg, not register unit
[all...] |
| LiveRegMatrix.h | 20 // in the physreg.
87 /// assigned to PhysReg or its aliases. This interference could be resolved
97 /// regmask operand that doesn't preserve PhysReg. This typically means
98 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
102 /// Check for interference before assigning VirtReg to PhysReg.
103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 /// Assign VirtReg to PhysReg.
110 /// update VirtRegMap. The live range is expected to be available in PhysReg.
111 void assign(LiveInterval &VirtReg, unsigned PhysReg);
[all...] |
| AllocationOrder.h | 66 /// isHint - Return true if PhysReg is a preferred register.
67 bool isHint(unsigned PhysReg) const { return PhysReg == Hint; }
|
| InterferenceCache.h | 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
100 PhysReg = 0;
106 unsigned getPhysReg() const { return PhysReg; }
114 /// valid - Return true if this is a valid entry for physReg
[all...] |
| RegAllocFast.cpp | 73 unsigned PhysReg; // Currently held here.
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
221 if (MO.getReg() == LR.PhysReg)
224 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
231 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &
[all...] |
| RegisterCoalescer.h | 57 /// is a physreg. This register class may be a super-register of both
66 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
68 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| RegisterClassInfo.cpp | 89 unsigned PhysReg = RawOrder[i];
91 if (Reserved.test(PhysReg))
93 if (CSRNum[PhysReg])
94 // PhysReg aliases a CSR, save it for later.
95 CSRAlias.push_back(PhysReg);
97 RCI.Order[N++] = PhysReg;
|
| VirtRegMap.cpp | 81 unsigned physReg = Hint.second;
82 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
83 physReg = getPhys(physReg);
85 return (TargetRegisterInfo::isPhysicalRegister(physReg))
86 ? physReg : 0;
87 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
235 // assigned PhysReg must be marked as live-in to those blocks.
236 unsigned PhysReg = VRM->getPhys(VirtReg)
[all...] |
| InterferenceCache.cpp | 38 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
39 unsigned E = PhysRegEntries[PhysReg];
40 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
56 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
57 PhysRegEntries[PhysReg] = E;
71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
75 void InterferenceCache::Entry::reset(unsigned physReg,
82 PhysReg = physReg;
88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
[all...] |
| RegAllocBasic.cpp | 114 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 // Spill or split all live virtual registers currently unified under PhysReg
169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
176 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
188 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
192 // Spill each interfering vreg allocated to PhysReg or an alias.
230 while (unsigned PhysReg = Order.next()) {
231 // Check for interference in PhysReg
232 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
234 // PhysReg is available, allocate it
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| RegAllocGreedy.cpp | 183 unsigned PhysReg;
188 // Interference for PhysReg.
196 PhysReg = Reg;
216 /// Candidate info for for each PhysReg in AllocationOrder.
442 unsigned PhysReg;
443 while ((PhysReg = Order.next()))
444 if (!Matrix->checkInterference(VirtReg, PhysReg))
446 if (!PhysReg || Order.isHint(PhysReg))
447 return PhysReg;
[all...] |
| LiveRangeCalc.h | 109 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
113 unsigned PhysReg);
164 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
165 void extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg = 0);
|
| LiveRangeCalc.cpp | 136 unsigned PhysReg) {
153 VNInfo *VNI = findReachingDefs(LI, KillMBB, Kill, PhysReg);
177 unsigned PhysReg) {
195 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
196 !MBB->isLiveIn(PhysReg)) {
|
| MachineRegisterInfo.cpp | 27 // Create the physreg use/def lists.
111 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
311 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
313 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
316 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
323 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 404 std::string PhysReg;
407 return PhysReg;
412 return PhysReg;
414 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
416 PhysReg += "::";
417 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
418 return PhysReg;
520 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
521 if (PhysReg.empty()) {
531 PhysRegInputs->push_back(PhysReg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 113 unsigned &PhysReg, int &Cost) {
126 PhysReg = Reg;
468 unsigned PhysReg = 0;
471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
472 assert((PhysReg == 0 || !isChain) &&
473 "Chain dependence via physreg data?");
480 PhysReg = 0;
489 OpLatency, PhysReg);
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
