| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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| Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl,
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
371 ARMCC::CondCodes Pred, unsigned PredReg,
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448 ARMCC::CondCodes Pred, unsigned PredReg,
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges)
[all...] |
| Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
180 ARMCC::CondCodes Pred, unsigned PredReg,
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
403 unsigned PredReg;
[all...] |
| Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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| ARMBaseInstrInfo.h | 358 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
379 ARMCC::CondCodes Pred, unsigned PredReg,
385 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMBaseRegisterInfo.cpp | 710 unsigned PredReg, unsigned MIFlags) const {
720 .addImm(0).addImm(Pred).addReg(PredReg)
749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
752 Pred, PredReg, TII);
755 Pred, PredReg, TII);
788 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
789 unsigned PredReg = Old->getOperand(2).getReg();
790 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
792 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
793 unsigned PredReg = Old->getOperand(3).getReg()
[all...] |
| MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg();
232 MIB.addImm(Pred).addReg(PredReg);
244 MIB.addImm(Pred).addReg(PredReg);
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| Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0;
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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| ARMBaseRegisterInfo.h | 169 unsigned PredReg = 0,
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| Thumb2SizeReduction.cpp | 544 unsigned PredReg = 0;
545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
643 unsigned PredReg = 0;
644 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
735 unsigned PredReg = 0;
736 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| Thumb1RegisterInfo.cpp | 70 ARMCC::CondCodes Pred, unsigned PredReg,
80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
413 unsigned PredReg;
414 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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| ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0;
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 303 unsigned PredReg = LastI->getOperand(1).getReg();
347 MI->getOperand(0).getReg() == PredReg) {
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