| /external/clang/test/SemaTemplate/ |
| nested-name-spec-template.cpp | 5 template<typename T> struct Promote;
7 template<> struct Promote<short> {
11 template<> struct Promote<int> {
15 template<> struct Promote<float> {
19 Promote<short>::type *ret_intptr(int* ip) { return ip; }
20 Promote<int>::type *ret_intptr2(int* ip) { return ip; }
23 M::Promote<int>::type *ret_intptr3(int* ip) { return ip; }
24 M::template Promote<int>::type *ret_intptr4(int* ip) { return ip; } // expected-warning{{'template' keyword outside of a template}}
25 M::template Promote<int> pi; // expected-warning{{'template' keyword outside of a template}}
28 N::M::Promote<int>::type *ret_intptr5(int* ip) { return ip;
[all...] |
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| toy.ml | 33 (* Promote allocas to registers. *)
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 114 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
115 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
116 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
303 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
304 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
334 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
335 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
336 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
351 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 453 // Promote the value if needed.
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 87 Promote, // This operation should be executed in a larger type.
281 /// it is already legal (return 'Legal') or we need to promote it to a larger
282 /// type (return 'Promote'), or we need to expand it into multiple registers
293 /// returns the larger type to promote to. For integer types that are larger
501 assert(Action != Promote && "Can't promote condition code!");
513 /// getTypeToPromoteTo - If the action for this operation is to promote, this
514 /// method returns the ValueType to promote to.
516 assert(getOperationAction(Op, VT) == Promote &&
532 "Didn't find type to promote to!")
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
731 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
472 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // VAARG always uses double-word chunks, so promote anything smaller.
236 setOperationAction(ISD::VAARG, MVT::i1, Promote);
238 setOperationAction(ISD::VAARG, MVT::i8, Promote);
240 setOperationAction(ISD::VAARG, MVT::i16, Promote);
242 setOperationAction(ISD::VAARG, MVT::i32, Promote);
285 // We cannot do this with Promote because i64 is not a legal type.
324 // We promote all shuffles to v16i8.
325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
328 // We promote all non-typed operations to v4i32
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 178 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
179 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 238 case TargetLowering::Promote:
241 // "Promote" the operation by bitcasting
247 // "Promote" the operation by extending the operand.
296 "Can't promote a vector with multiple results!");
318 "Can't promote a vector with multiple results!");
320 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
|
| LegalizeDAG.cpp | 188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
733 case TargetLowering::Promote: {
734 assert(VT.isVector() && "Unknown legal promote case!");
754 // Promote to a byte-sized store with upper bits zero if not
755 // storing an integral number of bytes. For example, promote
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 420 // Promote the value if needed.
704 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote);
99 setOperationAction(ISD::STORE, VT, Promote);
132 // Promote all bit-wise operations.
134 setOperationAction(ISD::AND, VT, Promote);
136 setOperationAction(ISD::OR, VT, Promote);
138 setOperationAction(ISD::XOR, VT, Promote);
581 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
