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    Searched refs:REG_SEQUENCE (Results 1 - 7 of 7) sorted by null

  /external/llvm/include/llvm/Target/
TargetOpcodes.h 71 /// REG_SEQUENCE - This variadic instruction is used to form a register that
75 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
78 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
81 REG_SEQUENCE = 12,
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 622 return getOpcode() == TargetOpcode::REG_SEQUENCE;
658 case TargetOpcode::REG_SEQUENCE:
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  /external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 267 case TargetOpcode::REG_SEQUENCE:
307 case TargetOpcode::REG_SEQUENCE:
InstrEmitter.cpp 592 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
601 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
604 "REG_SEQUENCE must have an odd number of operands!");
605 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
712 // Handle REG_SEQUENCE specially.
713 if (Opc == TargetOpcode::REG_SEQUENCE) {
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ScheduleDAGRRList.cpp 279 if (Opcode == TargetOpcode::REG_SEQUENCE) {
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  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 238 case TargetOpcode::REG_SEQUENCE:
283 case TargetOpcode::REG_SEQUENCE:
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 233 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
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