| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 29 const NVPTXRegisterInfo RegInfo;
33 virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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| VectorElementize.cpp | 65 const NVPTXRegisterInfo *RegInfo;
613 if (!RegInfo->isVirtualRegister(oper.getReg())) continue;
623 if (!RegInfo->isVirtualRegister(defSrc.getReg())) continue;
642 if (!(RegInfo->isVirtualRegister(oper.getReg())))
650 if (!(RegInfo->isVirtualRegister(defSrc.getReg())))
687 assert(RegInfo->isVirtualRegister(dest.getReg()) &&
708 RegInfo = TM.getRegisterInfo();
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 51 const Thumb1RegisterInfo *RegInfo =
60 unsigned FramePtr = RegInfo->getFrameRegister(MF);
61 unsigned BasePtr = RegInfo->getBaseRegister();
73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
159 if (RegInfo->needsStackRealignment(MF))
166 if (RegInfo->hasBasePointer(MF))
209 const Thumb1RegisterInfo *RegInfo =
216 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs()
[all...] |
| ARMFrameLowering.cpp | 44 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
54 RegInfo->needsStackRealignment(MF) ||
137 const ARMBaseRegisterInfo *RegInfo =
148 unsigned FramePtr = RegInfo->getFrameRegister(MF);
291 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
325 if (RegInfo->hasBasePointer(MF)) {
328 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
333 RegInfo->getBaseRegister())
352 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
361 unsigned FramePtr = RegInfo->getFrameRegister(MF)
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineFunction.cpp | 57 RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo());
59 RegInfo = 0;
79 if (RegInfo) {
80 RegInfo->~MachineRegisterInfo();
81 Allocator.Deallocate(RegInfo);
300 if (RegInfo) {
301 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
302 if (!RegInfo->tracksLiveness())
319 if (RegInfo && !RegInfo->livein_empty())
[all...] |
| MachineInstr.cpp | 133 MachineRegisterInfo *RegInfo = 0;
137 RegInfo = &MF->getRegInfo();
141 if (RegInfo && WasReg)
142 RegInfo->removeRegOperandFromUseList(this);
164 if (RegInfo)
165 RegInfo->addRegOperandToUseList(this);
667 MachineRegisterInfo *RegInfo = getRegInfo();
670 // be removed and re-added to RegInfo. It is storing pointers to operands.
671 bool Reallocate = RegInfo &&
678 // Remove all the implicit operands from RegInfo if they need to be shifted
[all...] |
| PrologEpilogInserter.cpp | 153 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
200 RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
208 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
248 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
251 if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
560 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
561 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) &&
562 !RegInfo->needsStackRealignment(Fn)) {
644 if (RS && (!TFI.hasFP(Fn) || RegInfo->needsStackRealignment(Fn) |
[all...] |
| MachineInstrBundle.cpp | 251 MachineOperandIteratorBase::RegInfo
254 RegInfo RI = { false, false, false };
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
51 RegInfo->needsStackRealignment(MF) ||
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
650 unsigned SlotSize = RegInfo->getSlotSize();
651 unsigned FramePtr = RegInfo->getFrameRegister(MF);
652 unsigned StackPtr = RegInfo->getStackRegister();
653 unsigned BasePtr = RegInfo->getBaseRegister()
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBundle.h | 133 /// RegInfo - Information about a virtual register used by a set of operands.
135 struct RegInfo {
156 /// @returns A filled-in RegInfo struct.
157 RegInfo analyzeVirtReg(unsigned Reg,
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| MachineInstr.h | [all...] |
| MachineFunction.h | 81 // RegInfo - Information about each register in use in the function.
82 MachineRegisterInfo *RegInfo;
160 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
161 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| FunctionLoweringInfo.h | 59 MachineRegisterInfo *RegInfo;
|
| SelectionDAGISel.h | 49 MachineRegisterInfo *RegInfo;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 34 const MipsRegisterInfo *RegInfo =
90 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
91 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
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| MipsISelLowering.cpp | [all...] |
| MipsISelDAGToDAG.cpp | 125 MachineRegisterInfo &RegInfo = MF.getRegInfo();
138 V0 = RegInfo.createVirtualRegister(RC);
139 V1 = RegInfo.createVirtualRegister(RC);
140 V2 = RegInfo.createVirtualRegister(RC);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 287 MachineRegisterInfo &RegInfo = MF->getRegInfo();
290 GlobalBaseReg = RegInfo.createVirtualRegister(&MBlaze::GPRRegClass);
293 RegInfo.addLiveIn(MBlaze::R20);
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 41 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
48 const MCRegisterInfo *getRegInfo() const { return RegInfo; }
51 const MCRegisterInfo *RegInfo;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 191 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
193 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
212 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
213 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
258 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
262 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 347 MachineRegisterInfo &RegInfo = MF->getRegInfo();
349 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 341 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
360 if (RegInfo->requiresRegisterScavenging(MF)) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 348 RegInfo = &MF->getRegInfo();
373 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
377 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
378 E = RegInfo->livein_end(); LI != E; ++LI)
389 MachineInstr *Def = RegInfo->getVRegDef(Reg);
398 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
414 UI = RegInfo->use_begin(LDI->second);
[all...] |
| FunctionLoweringInfo.cpp | 65 RegInfo = &MF->getRegInfo();
212 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
|
