/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 728 MVT RegVT = VA.getLocVT(); 736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 742 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 327 EVT RegVT = VA.getLocVT(); 328 switch (RegVT.getSimpleVT().SimpleTy) { 333 << RegVT.getSimpleVT().SimpleTy << "\n"; 340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 268 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), 274 EVT RegVT;
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SelectionDAGBuilder.cpp | 584 EVT regvt, EVT valuevt) 585 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} [all...] |
LegalizeVectorOps.cpp | 405 EVT RegVT = Value.getValueType(); 406 EVT RegSclVT = RegVT.getScalarType();
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LegalizeDAG.cpp | 324 EVT RegVT = 329 unsigned RegBytes = RegVT.getSizeInBits() / 8; 333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 452 unsigned RegBytes = RegVT.getSizeInBits() / 8; 456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr [all...] |
LegalizeIntegerTypes.cpp | 698 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 700 // The argument is passed as NumRegs registers of type RegVT. 704 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 720 DAG.getConstant(i * RegVT.getSizeInBits(), [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 845 EVT RegVT = VA.getLocVT(); 846 if (RegVT == MVT::i8 || RegVT == MVT::i16 || 847 RegVT == MVT::i32 || RegVT == MVT::f32) { 851 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 852 } else if (RegVT == MVT::i64) { 856 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |