| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerProxy.h | 59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
60 virtual uint32_t reg_rrx(int Rm);
61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
65 // (immediate and Rm can be negative, which indicates U=0)
68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
72 // (immediate and Rm can be negative, which indicates U=0)
75 virtual uint32_t reg_pre(int Rm, int W=0);
76 virtual uint32_t reg_post(int Rm);
83 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerInterface.h | 81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
82 virtual uint32_t reg_rrx(int Rm) = 0;
83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
87 // (immediate and Rm can be negative, which indicates U=0)
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
94 // (immediate and Rm can be negative, which indicates U=0)
97 virtual uint32_t reg_pre(int Rm, int W=0) = 0;
98 virtual uint32_t reg_post(int Rm) = 0;
128 int Rd, int Rm, int Rs, int Rn) = 0
[all...] |
| ARMAssembler.cpp | 229 int Rd, int Rm, int Rs, int Rn) {
230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
236 int Rd, int Rm, int Rs) {
237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
[all...] |
| ARMAssemblerProxy.cpp | 93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift)
95 return mTarget->reg_imm(Rm, type, shift);
98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm)
100 return mTarget->reg_rrx(Rm);
103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs)
105 return mTarget->reg_reg(Rm, type, Rs);
111 // (immediate and Rm can be negative, which indicates U=0)
122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W)
124 return mTarget->reg_scale_pre(Rm, type, shift, W);
127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, int type, uint32_t shift
[all...] |
| ARMAssembler.h | 71 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
72 virtual uint32_t reg_rrx(int Rm);
73 virtual uint32_t reg_reg(int Rm, int type, int Rs);
77 // (immediate and Rm can be negative, which indicates U=0)
80 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
81 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
84 // (immediate and Rm can be negative, which indicates U=0)
87 virtual uint32_t reg_pre(int Rm, int W=0);
88 virtual uint32_t reg_post(int Rm);
95 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPSAssembler.h | 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
69 virtual uint32_t reg_rrx(int Rm);
70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
74 // (immediate and Rm can be negative, which indicates U=0)
77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
81 // (immediate and Rm can be negative, which indicates U=0)
84 virtual uint32_t reg_pre(int Rm, int W=0);
85 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPSAssembler.cpp | 234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
236 amode.reg = Rm;
242 uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
256 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
277 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
282 amode.reg = Rm;
289 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
295 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W
[all...] |
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/ |
| trace.c | 894 int Rm = (insn & 15);
905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs);
909 int Rm = (insn & 15);
920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs);
924 int Rm = (insn & 15);
927 result = 2 + _interlock_use(Rm);
932 int Rm = (insn & 15);
936 result += _interlock_use(Rn) + _interlock_use(Rm);
955 int Rm = (insn & 15);
959 result += _interlock_use(Rn) + _interlock_use(Rm);
[all...] |
| i386-dis.c | 349 #define Rm { OP_R, m_mode }
1581 int rm; member in struct:__anon12548
[all...] |
| arm-dis.c | 2070 const char *rm = arm_regnames [given & 0xf]; local
2285 int rm = ((given >> 0) & 0xf); local
2315 int rm = ((given >> 0) & 0xf); local
2390 int rm = ((given >> 0) & 0xf); local
[all...] |
| /external/qemu/distrib/sdl-1.2.15/src/video/ |
| SDL_pixels.c | 143 int Rm=0,Gm=0,Bm=0;
152 Rm|=1<<i;
155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm);
189 r=(r<<format->Rloss)|((r*Rm)>>Rw);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 709 // [Rn, Rm]
710 // {5-3} = Rm
715 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
716 return (Rm << 3) | Rn;
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 214 int rm = instr->RmValue(); local
216 PrintRegister(rm);
219 // Special case for using rm only.
336 } else if (format[1] == 'm') { // 'rm: Rm register
693 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
707 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
708 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs")
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| vfp.stdout.exp | [all...] |
| v6intThumb.stdout.exp | 2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
[all...] |
