| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 47 /// SDValue if the target declines to use custom code and a different
56 virtual SDValue
58 SDValue Chain,
59 SDValue Op1, SDValue Op2,
60 SDValue Op3, unsigned Align, bool isVolatile,
64 return SDValue();
71 /// SDValue if the target declines to use custom code and a different
73 virtual SDValue
75 SDValue Chain
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.h | 67 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
69 std::vector<SDValue> &OutOps);
78 inline SDValue getI32Imm(unsigned Imm) {
83 bool SelectDirectAddr(SDValue N, SDValue &Address);
85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
86 SDValue &Offset, MVT mvt);
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base
[all...] |
| NVPTXISelLowering.h | 71 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
102 virtual SDValue
103 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
106 SmallVectorImpl<SDValue> &InVals) const;
108 virtual SDValue
109 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 83 DenseMap<SDValue, SDValue> PromotedIntegers;
87 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
91 DenseMap<SDValue, SDValue> SoftenedFloats;
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats
[all...] |
| InstrEmitter.h | 44 DenseMap<SDValue, unsigned> &VRBaseMap);
54 DenseMap<SDValue, unsigned> &VRBaseMap);
58 unsigned getVR(SDValue Op,
59 DenseMap<SDValue, unsigned> &VRBaseMap);
64 void AddRegisterOperand(MachineInstr *MI, SDValue Op,
67 DenseMap<SDValue, unsigned> &VRBaseMap,
74 void AddOperand(MachineInstr *MI, SDValue Op,
77 DenseMap<SDValue, unsigned> &VRBaseMap,
88 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
96 DenseMap<SDValue, unsigned> &VRBaseMap)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.h | 37 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
38 SDValue Chain,
39 SDValue Dst, SDValue Src,
40 SDValue Size, unsigned Align,
45 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
46 SDValue Chain,
47 SDValue Dst, SDValue Src,
48 SDValue Size, unsigned Align
[all...] |
| X86ISelLowering.h | 427 bool isZeroNode(SDValue Elt);
458 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
499 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
504 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
508 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
520 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
537 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
545 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSelectionDAGInfo.h | 29 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
|
| HexagonISelLowering.h | 71 IsEligibleForTailCallOptimization(SDValue Callee,
78 const SmallVectorImpl<SDValue> &OutVals,
85 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
[all...] |
| HexagonSelectionDAGInfo.cpp | 28 SDValue
30 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain,
31 SDValue Dst, SDValue Src, SDValue Size, unsigned Align,
45 return SDValue();
|
| HexagonISelDAGToDAG.cpp | 55 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
56 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
57 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
58 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 148 SDValue Root;
289 const SDValue &getRoot() const { return Root; }
293 SDValue getEntryNode() const {
294 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
299 const SDValue &setRoot(SDValue N) {
365 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
366 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
367 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
368 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false)
[all...] |
| SelectionDAGISel.h | 26 class SDValue;
85 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
87 std::vector<SDValue> &OutOps) {
93 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
99 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
177 void ReplaceUses(SDValue F, SDValue T) {
183 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
196 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 239 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
260 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
261 SDValue &Offset,
268 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
274 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
279 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 48 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
49 SDValue Chain,
50 SDValue Dst, SDValue Src,
51 SDValue Size, unsigned Align,
58 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
59 SDValue Chain,
60 SDValue Op1, SDValue Op2,
61 SDValue Op3, unsigned Align
[all...] |
| ARMISelLowering.h | 253 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
258 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
278 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
279 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
313 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
314 SDValue &Offset,
322 SDValue &Base, SDValue &Offset,
326 virtual void computeMaskedBitsForTargetNode(const SDValue Op
[all...] |
| ARMISelDAGToDAG.cpp | 83 inline SDValue getI32Imm(unsigned Imm) {
91 bool isShifterOpProfitable(const SDValue &Shift,
93 bool SelectRegShifterOperand(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C,
96 bool SelectImmShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, bool CheckProfitability = true);
98 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
92 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
111 SDValue LowerCCCArguments(SDValue Chain,
116 SmallVectorImpl<SDValue> &InVals) const;
117 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
121 const SmallVectorImpl<SDValue> &OutVals
[all...] |
| XCoreISelDAGToDAG.cpp | 54 inline SDValue getI32Imm(unsigned Imm) {
70 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
71 bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
72 bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 98 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
117 SmallVectorImpl<SDValue> &InVals) const;
120 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
[all...] |
| MBlazeISelDAGToDAG.cpp | 85 bool SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index);
86 bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base);
89 inline SDValue getI32Imm(unsigned Imm) {
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
121 SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 109 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
118 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
126 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
130 SmallVectorImpl<SDValue> &InVals) const;
133 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
52 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
70 virtual SDValue
71 LowerFormalArguments(SDValue Chain,
76 SmallVectorImpl<SDValue> &InVals) const;
78 virtual SDValue
80 SmallVectorImpl<SDValue> &InVals) const;
82 virtual SDValue
83 LowerReturn(SDValue Chain
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
80 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat
[all...] |
