| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 330 /// Much like the scalar select and setcc, each bit in the condition selects
343 /// SetCC operator - This evaluates to a true value iff the condition is
349 SETCC,
497 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| SelectionDAG.h | 605 /// getSetCC - Helper function to make it easier to build SetCC's if you just
614 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 31 SETCC,
|
| HexagonISelDAGToDAG.cpp | 819 if (N0.getOpcode() == ISD::SETCC) {
828 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
852 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
[all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
189 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 200 case ISD::SETCC:
271 else if (Node->getOpcode() == ISD::SETCC)
606 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
308 // Turn it into a scalar SETCC.
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
335 // Turn it into a scalar SETCC.
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
492 case ISD::SETCC:
[all...] |
| DAGCombiner.cpp | 531 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
532 // that selects between the values 1 and 0, making it equivalent to a setcc.
538 if (N.getOpcode() == ISD::SETCC) {
557 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| LegalizeFloatTypes.cpp | 591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
611 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
618 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
675 default: llvm_unreachable("Do not know how to soften this setcc!");
686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
[all...] |
| SelectionDAGDumper.cpp | 187 case ISD::SETCC: return "setcc";
287 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeDAG.cpp | 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
494 // Promote all the way up to the canonical SetCC type.
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| SelectionDAG.cpp | 251 /// 'op' is a valid SetCC operation.
271 default: llvm_unreachable("Illegal integer setcc operation!");
292 // Cannot fold a signed integer setcc with an unsigned integer setcc.
302 // Canonicalize illegal integer setcc's.
316 // Cannot fold a signed setcc with an unsigned setcc.
322 // Canonicalize illegal integer setcc's.
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| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
449 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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| X86ISelLowering.h | 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
91 SETCC,
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
531 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 321 setOperationAction(ISD::SETCC, MVT::i8, Legal);
322 setOperationAction(ISD::SETCC, MVT::i16, Legal);
323 setOperationAction(ISD::SETCC, MVT::i32, Legal);
324 setOperationAction(ISD::SETCC, MVT::i64, Legal);
325 setOperationAction(ISD::SETCC, MVT::f64, Custom);
513 // Return the Cell SPU's SETCC result type
517 // i8, i16 and i32 are valid SETCC result types
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 735 // Sparc has no select or setcc: expand to SELECT_CC.
739 setOperationAction(ISD::SETCC, MVT::i32, Expand);
740 setOperationAction(ISD::SETCC, MVT::f32, Expand);
741 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 104 // setcc operations results (slt, sgt, ...).
140 // Used by legalize types to correctly generate the setcc result.
141 // Without this, every float setcc comes with a AND/OR with the result,
144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
157 setOperationAction(ISD::SETCC, MVT::f32, Custom);
158 setOperationAction(ISD::SETCC, MVT::f64, Custom);
573 // Creates and returns an FPCmp node from a setcc node.
574 // Returns Op if setcc is not a floating point comparison.
576 // must be a SETCC node
577 if (Op.getOpcode() != ISD::SETCC)
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 60 // setcc operations results (slt, sgt, ...).
138 // Used by legalize types to correctly generate the setcc result.
139 // Without this, every float setcc comes with a AND/OR with the result,
142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
364 // setcc r1, r2, r3
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 589 /// associated with the SetCC condition, and whether or not the field is
632 // We can codegen setcc op, imm very efficiently compared to a brcond.
634 // setcc op, 0
664 } else if (Imm == ~0U) { // setcc op, -1
834 case ISD::SETCC:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 105 setOperationAction(ISD::SETCC, VT, Custom);
484 // FIXME: Code duplication: SETCC has custom operation action, see
486 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
531 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 81 // Use i32 for setcc operations results (slt, sgt, ...).
216 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
[all...] |
