| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
[all...] |
| MIPSAssembler.h | 317 void SRA(int Rd, int Rt, int shft);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 316 SHL, SRA, SRL, ROTL, ROTR,
380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 95 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
185 case ISD::SRA: return LowerShifts(Op, DAG);
604 case ISD::SRA:
605 return DAG.getNode(MSP430ISD::SRA, dl,
824 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 245 case SRA:
|
| constants-mips.h | 306 SRA = ((0 << 3) + 3),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
[all...] |
| DAGCombiner.cpp | [all...] |
| FastISel.cpp | 391 // Transform "sdiv exact X, 8" -> "sra X, 3".
396 ISDOpcode = ISD::SRA;
[all...] |
| SelectionDAGBuilder.h | 491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
| SelectionDAGDumper.cpp | 172 case ISD::SRA: return "sra";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
188 case ISD::SRA:
|
| SelectionDAG.cpp | [all...] |
| /hardware/ti/wlan/wl1271/external_drivers/sdio/linux/ |
| SdioDrv.c | 115 #define SRA (1 << 24)
518 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | SRA);
519 while ((status = OMAP_HSMMC_READ(SYSCTL) & SRA) && loops++ < SDIODRV_MAX_LOOPS);
520 if (status & SRA)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 244 setOperationAction(ISD::SRA, MVT::i8, Custom);
249 setOperationAction(ISD::SRA, MVT::i64, Legal);
[all...] |
| SPUISelDAGToDAG.cpp | 232 //! Emit the instruction sequence for i64 sra
742 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
745 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
781 } else if (Opc == ISD::SRA) {
[all...] |
| /external/llvm/lib/TableGen/ |
| Record.cpp | 925 case SRA:
935 case SRA: Result = LHSv >> RHSv; break;
960 case SRA: Result = "!sra"; break;
[all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 125 case 0x01: return MBlaze::SRA;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 644 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 267 // sra dst, dst
323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
447 // sra dst, dst
[all...] |
