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    Searched refs:SUBREG_TO_REG (Results 1 - 9 of 9) sorted by null

  /external/llvm/include/llvm/Target/
TargetOpcodes.h 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
58 SUBREG_TO_REG = 9,
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 619 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
657 case TargetOpcode::SUBREG_TO_REG:
    [all...]
  /external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
100 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
120 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
218 case TargetOpcode::SUBREG_TO_REG:
PeepholeOptimizer.cpp 207 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
214 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
216 // The problem here is that SUBREG_TO_REG is there to assert that an
220 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
  /external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 266 case TargetOpcode::SUBREG_TO_REG:
306 case TargetOpcode::SUBREG_TO_REG:
InstrEmitter.cpp 516 Opc == TargetOpcode::SUBREG_TO_REG) {
543 // Create the insert_subreg or subreg_to_reg machine instruction.
547 // If creating a subreg_to_reg, then the first input operand
549 if (Opc == TargetOpcode::SUBREG_TO_REG) {
561 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
701 Opc == TargetOpcode::SUBREG_TO_REG) {
    [all...]
ScheduleDAGRRList.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 237 case TargetOpcode::SUBREG_TO_REG:
282 case TargetOpcode::SUBREG_TO_REG:
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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