| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 198 unsigned SubReg = *SubRegs;
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs;
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg = *SubRegs
[all...] |
| MachineInstrBundle.cpp | 173 unsigned SubReg = *SubRegs;
174 if (LocalDefSet.insert(SubReg))
175 LocalDefs.push_back(SubReg);
|
| MachineInstr.cpp | 147 SubReg = 0;
[all...] |
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 36 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
41 if (*Subs == SubReg)
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 223 const char *const *SubRegIndexNames; // Names of subreg indexes.
463 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
468 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
[all...] |
| TargetInstrInfo.h | 110 /// true, then it's expected the pre-extension value is available as a subreg
183 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 65 /// SubReg - Subregister number, only valid for MO_Register. A value of 0
66 /// indicates the MO_Register has no subReg.
67 unsigned char SubReg;
264 return (unsigned)SubReg;
337 void setSubReg(unsigned subReg) {
339 SubReg = (unsigned char)subReg;
343 /// subregister Reg:SubReg. Take any existing SubReg index into account,
344 /// using TargetRegisterInfo to compose the subreg indices if necessary
[all...] |
| MachineInstrBuilder.h | 60 unsigned SubReg = 0) const {
70 SubReg,
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 336 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
338 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 352 0/*SubReg*/, IsDebug));
453 /// EmitSubregNode - Generate machine code for subreg nodes.
614 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
615 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
698 // Handle subreg insert/extract specially
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 243 // Expand any composed subreg indices.
245 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
246 // expanded subreg indices recursively.
261 // Add I->second as a name for the subreg SRI->second, assuming it is
274 // Consider this subreg sequence:
285 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
297 // Compute the inverse SubReg -> Idx map.
410 const CodeGenRegister *SubReg = I->second;
411 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 526 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
528 O << ARMInstPrinter::getRegisterName(SubReg);
[all...] |
