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    Searched refs:TCG_REG_R0 (Results 1 - 8 of 8) sorted by null

  /external/qemu/tcg/ppc64/
tcg-target.h 31 TCG_REG_R0 = 0,
tcg-target.c     [all...]
  /external/qemu/tcg/arm/
tcg-target.c 101 TCG_REG_R0,
110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
113 TCG_REG_R0, TCG_REG_R1
177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
198 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
208 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
996 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
997 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
998 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1007 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0
    [all...]
tcg-target.h 32 TCG_REG_R0 = 0,
  /external/qemu/tcg/ppc/
tcg-target.h 31 TCG_REG_R0 = 0,
tcg-target.c     [all...]
  /external/qemu/tcg/hppa/
tcg-target.h 38 TCG_REG_R0 = 0,
tcg-target.c 40 #define TCG_GUEST_BASE_REG TCG_REG_R0
347 | INSN_R2(TCG_REG_R0));
356 | INSN_R2(TCG_REG_R0) | INSN_IM14(arg));
379 if (addr == TCG_REG_R0) {
441 tcg_out_arith(s, TCG_REG_R0, TCG_REG_R0, TCG_REG_R0, INSN_OR);
569 tcg_out_vshd(s, ret, TCG_REG_R0, arg, creg);
823 tcg_out_comclr(s, tcg_invert_cond(cond), TCG_REG_R0, al, bl, blconst);
829 tcg_out_comclr(s, TCG_COND_NE, TCG_REG_R0, ah, bh, bhconst)
    [all...]

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