| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.h | 24 const MipsSEInstrInfo &TII;
28 const MipsSEInstrInfo &TII);
|
| Mips16FrameLowering.cpp | 32 const MipsInstrInfo &TII =
43 BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
50 const MipsInstrInfo &TII =
61 BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
|
| MipsLongBranch.cpp | 68 TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
88 const MipsInstrInfo *TII;
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode());
221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
292 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT
[all...] |
| MipsSEFrameLowering.cpp | 36 const MipsSEInstrInfo &TII =
56 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
61 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
78 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
110 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
115 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
126 const MipsSEInstrInfo &TII =
143 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
153 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
163 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo()
[all...] |
| MipsSERegisterInfo.cpp | 44 : MipsRegisterInfo(ST), TII(I) {}
59 const MipsSEInstrInfo *II = static_cast<const MipsSEInstrInfo*>(&TII);
128 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
129 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 66 const HexagonInstrInfo *TII = QTM.getInstrInfo();
87 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
88 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
90 TII->get(Hexagon::CONST32_Int_Real),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
98 TII->get(Hexagon::STriw_indexed))
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
107 TII->get(Hexagon::STriw_indexed)
[all...] |
| HexagonSplitTFRCondSets.cpp | 74 const TargetInstrInfo *TII = QTM.getInstrInfo();
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
126 TII->get(Hexagon::TFR_cPt), DestReg).
131 TII->get(Hexagon::TFRI_cNotPt), DestReg).
136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
152 TII->get(Hexagon::TFRI_cPt), DestReg).
157 TII->get(Hexagon::TFRI_cPt_f), DestReg).
166 TII->get(Hexagon::TFR_cNotPt), DestReg).
182 TII->get(Hexagon::TFRI_cPt)
[all...] |
| HexagonRegisterInfo.cpp | 41 const HexagonInstrInfo &tii)
44 TII(tii) {
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
168 !TII.isSpillPredRegOp(&MI)) {
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
196 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
200 TII.get(Hexagon::ADD_rr),
204 TII.get(Hexagon::ADD_ri)
[all...] |
| HexagonFrameLowering.cpp | 145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
187 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
196 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
199 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
229 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
260 TII.storeRegToStackSlot(MBB, MI, SuperReg, true
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 32 const SparcInstrInfo &TII =
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
73 const SparcInstrInfo &TII =
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 31 const ARMBaseInstrInfo &TII;
40 const ARMBaseInstrInfo &tii,
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
|
| Thumb1FrameLowering.cpp | 39 const TargetInstrInfo &TII, DebugLoc dl,
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
53 const Thumb1InstrInfo &TII =
73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
135 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
167 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
211 const Thumb1InstrInfo &TII =
221 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes)
[all...] |
| Thumb1RegisterInfo.cpp | 43 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
45 : ARMBaseRegisterInfo(tii, sti) {
78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
95 const TargetInstrInfo &TII,
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
171 int NumBytes, const TargetInstrInfo &TII,
231 TII, MRI, MIFlags)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 95 const SPUInstrInfo &TII =
120 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
140 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
142 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
145 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
148 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2
[all...] |
| SPUNopFiller.cpp | 31 const TargetInstrInfo *TII;
37 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()),
96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 56 const PPCInstrInfo *TII =
71 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
152 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCHazardRecognizers.h | 46 const TargetInstrInfo &TII;
67 PPCHazardRecognizer970(const TargetInstrInfo &TII);
|
| PPCFrameLowering.cpp | 98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
258 const PPCInstrInfo &TII =
273 HandleVRSaveUpdate(MBBI, TII);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 48 const TargetInstrInfo &TII) {
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
63 const TargetInstrInfo &TII) {
70 BuildMI(MBB, I, dl, TII.get(Opcode))
95 const XCoreInstrInfo &TII =
105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
141 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
155 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
160 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel)
[all...] |
| XCoreRegisterInfo.cpp | 40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
234 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
255 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 55 const MSP430InstrInfo *TII =
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII =
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
110 const MSP430InstrInfo &TII =
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
161 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| MSP430RegisterInfo.cpp | 36 const TargetInstrInfo &tii)
37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
123 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
125 TII.get(MSP430::SUB16ri), MSP430::SPW)
128 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
134 TII.get(MSP430::ADD16ri), MSP430::SPW)
146 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
152 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
201 MI.setDesc(TII.get(MSP430::MOV16rr))
[all...] |
| MSP430RegisterInfo.h | 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.h | 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
|
