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    Searched refs:ValueVT (Results 1 - 2 of 2) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 92 EVT PartVT, EVT ValueVT);
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
101 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 if (ValueVT.isVector())
104 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
112 if (ValueVT.isInteger()) {
114 unsigned ValueBits = ValueVT.getSizeInBits();
121 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
162 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &
    [all...]
FunctionLoweringInfo.cpp 228 EVT ValueVT = ValueVTs[Value];
229 EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
231 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);

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