| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 82 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
83 addRegisterClass(MVT::i8, &NVPTX::Int8RegsRegClass);
84 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
85 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
86 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
87 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
88 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
91 addRegisterClass(MVT::v2f32, &NVPTX::V2F32RegsRegClass);
92 addRegisterClass(MVT::v4f32, &NVPTX::V4F32RegsRegClass);
93 addRegisterClass(MVT::v2i32, &NVPTX::V2I32RegsRegClass)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 105 addRegisterClass(MVT::i8, &SPU::R8CRegClass);
106 addRegisterClass(MVT::i16, &SPU::R16CRegClass);
107 addRegisterClass(MVT::i32, &SPU::R32CRegClass);
108 addRegisterClass(MVT::i64, &SPU::R64CRegClass);
109 addRegisterClass(MVT::f32, &SPU::R32FPRegClass);
110 addRegisterClass(MVT::f64, &SPU::R64FPRegClass);
111 addRegisterClass(MVT::i128, &SPU::GPRCRegClass);
402 addRegisterClass(MVT::v16i8, &SPU::VECREGRegClass);
403 addRegisterClass(MVT::v8i16, &SPU::VECREGRegClass);
404 addRegisterClass(MVT::v4i32, &SPU::VECREGRegClass)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 697 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
698 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
699 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass);
67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 224 addRegisterClass(MVT::i8, &X86::GR8RegClass);
225 addRegisterClass(MVT::i16, &X86::GR16RegClass);
226 addRegisterClass(MVT::i32, &X86::GR32RegClass);
228 addRegisterClass(MVT::i64, &X86::GR64RegClass);
576 addRegisterClass(MVT::f32, &X86::FR32RegClass);
577 addRegisterClass(MVT::f64, &X86::FR64RegClass);
608 addRegisterClass(MVT::f32, &X86::FR32RegClass);
609 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
641 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
642 addRegisterClass(MVT::f32, &X86::RFP32RegClass)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
116 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
120 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
125 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
127 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
377 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
378 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
379 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
380 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 69 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 152 addRegisterClass(VT, &ARM::DPRRegClass);
157 addRegisterClass(VT, &ARM::QPRRegClass);
430 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
432 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
435 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
437 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
[all...] |
