/external/llvm/lib/Transforms/Instrumentation/ |
PathProfiling.cpp | 11 // profiling converts the CFG into a DAG by replacing backedges with edges 13 // along the new DAG are enumrated, i.e. each path is given a path number. 20 // requirements are formatting the llvm CFG into the Ball-Larus DAG, path 25 // DAG - Directed Acyclic Graph. 26 // Ball-Larus DAG - A CFG with an entry node, an exit node, and backedges 30 // Ball-Larus DAG. 195 // Calculates a spanning tree of the DAG ignoring cycles. Whichever 316 BLInstrumentationDag* dag, 332 BLInstrumentationDag* dag); 336 bool splitCritical(BLInstrumentationEdge* edge, BLInstrumentationDag* dag); 1272 BLInstrumentationDag dag = BLInstrumentationDag(F); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers. 39 SelectionDAG *DAG; // DAG of the current basic block 51 void Run(SelectionDAG *dag, MachineBasicBlock *bb); 82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===// 83 /// CurDebugLoc - current file + line number. Changes as we build the DAG. 287 SelectionDAG &DAG; 322 /// no subsequent DAG nodes should be created. 328 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, 330 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 331 DAG(dag), FuncInfo(funcinfo), OptLevel(ol), 354 /// getRoot - Return the current virtual root of the Selection DAG, [all...] |
LegalizeVectorOps.cpp | 36 SelectionDAG& DAG; 81 VectorLegalizer(SelectionDAG& dag) : 82 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 92 DAG.AssignTopologicalOrder(); 93 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 94 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 98 SDValue OldRoot = DAG.getRoot(); 100 DAG.setRoot(LegalizedNodes[OldRoot]) [all...] |
LegalizeTypes.h | 1 //===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===// 37 SelectionDAG &DAG; 68 return TLI.getTypeAction(*DAG.getContext(), VT); 73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; 119 explicit DAGTypeLegalizer(SelectionDAG &dag) 120 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 127 /// top-down traversal of the dag, legalizing types as it goes. Returns 138 SelectionDAG &getDAG() const { return DAG; } [all...] |
ScheduleDAGSDNodes.cpp | 49 : ScheduleDAG(mf), BB(0), DAG(0), 54 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) { 56 DAG = dag; 58 // Clear the scheduler's SUnit DAG. 79 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 135 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, 145 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size()); 155 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size()); 162 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { [all...] |
LegalizeDAG.cpp | 52 SelectionDAG &DAG; 63 explicit SelectionDAGLegalize(SelectionDAG &DAG); 156 DAG.RemoveDeadNode(N); 162 DAG.ReplaceAllUsesWith(Old, New); 166 DAG.ReplaceAllUsesWith(Old, New); 170 DAG.ReplaceAllUsesWith(Old, New); 191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 209 : SelectionDAG::DAGUpdateListener(dag), [all...] |
/external/llvm/utils/vim/ |
tablegen.vim | 17 syn keyword tgKeyword def let in code dag field include defm foreach
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/external/llvm/lib/TableGen/ |
TGLexer.cpp | 274 .Case("dag", tgtok::Dag)
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/external/llvm/include/llvm/Target/ |
TargetLowering.h | 621 /// hasTargetDAGCombine - If true, the target has custom DAG combine [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 315 // Release all DAG roots for scheduling. 337 /// only includes instructions that have DAG nodes, not scheduling boundaries. 353 // Build the DAG, and compute current register pressure. 381 // Release all DAG roots for scheduling. 461 void ConvergingVLIWScheduler::initialize(VLIWMachineScheduler *dag) { 462 DAG = dag; 463 TRI = DAG->TRI; 464 Top.DAG = dag; [all...] |
HexagonMachineScheduler.h | 51 /// Initialize the strategy after building the DAG for a new region. 52 virtual void initialize(VLIWMachineScheduler *DAG) = 0; 339 VLIWMachineScheduler *DAG; 360 DAG(0), Available(ID, Name+".A"), 390 VLIWMachineScheduler *DAG; 406 DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} 408 virtual void initialize(VLIWMachineScheduler *dag);
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/external/llvm/ |
tblgen-rules.mk | 97 $(call transform-td-to-out,dag-isel)
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llvm-tblgen-rules.mk | 153 $(call transform-td-to-out,dag-isel)
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/ndk/sources/host-tools/nawk-20071023/ |
FIXES | 222 dag-erling smorgrav, des@ofug.org). subject to reversion if 248 portable. thanks to dag-erling smorgrav for code. [all...] |
/external/llvm/lib/CodeGen/ |
MachineScheduler.cpp | 165 /// consistent with the DAG builder, which traverses the interior of the 168 /// This design avoids exposing scheduling boundaries to the DAG builder, 169 /// simplifying the DAG builder's support for "special" target instructions. 216 // boundary at the bottom of the region. The DAG does not include RegionEnd, 300 /// Initialize the strategy after building the DAG for a new region. 301 virtual void initialize(ScheduleDAGMI *DAG) = 0; 590 // Release all DAG roots for scheduling. 612 /// only includes instructions that have DAG nodes, not scheduling boundaries. 621 // Build the DAG, and compute current register pressure. 638 // Release all DAG roots for scheduling [all...] |
/external/libpcap/ |
configure | [all...] |
/prebuilts/tools/common/eclipse/ |
org.eclipse.ui.workbench.texteditor_3.6.1.r361_v20100714-0800.jar | |