| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
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| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 179 if (RCI.getSubReg() == Idx)
218 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
227 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
237 *BestPreA = IA.getSubReg();
238 *BestPreB = IB.getSubReg();
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| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 64 sub = mi->getOperand(0).getSubReg();
66 hsub = mi->getOperand(1).getSubReg();
68 sub = mi->getOperand(1).getSubReg();
70 hsub = mi->getOperand(0).getSubReg();
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| OptimizePHIs.cpp | 106 !SrcMI->getOperand(0).getSubReg() &&
107 !SrcMI->getOperand(1).getSubReg() &&
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| TargetInstrInfoImpl.cpp | 81 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
82 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
83 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
259 if (FoldOp.getSubReg() || LiveOp.getSubReg())
394 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
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| VirtRegMap.cpp | 285 if (MO.getSubReg()) {
307 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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| ExpandPostRAPseudos.cpp | 104 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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| MachineInstr.cpp | 73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82 if (getSubReg()) {
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
179 getSubReg() == Other.getSubReg();
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
267 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| RegAllocFast.cpp | 659 if (!MO.getSubReg()) {
665 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
696 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
734 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| PHIElimination.cpp | 210 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
296 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
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| PeepholeOptimizer.cpp | 200 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
423 if (!MI->getOperand(0).getSubReg() &&
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| RegisterCoalescer.cpp | 207 DstSub = MI->getOperand(0).getSubReg();
209 SrcSub = MI->getOperand(1).getSubReg();
212 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
215 SrcSub = MI->getOperand(2).getSubReg();
246 Dst = TRI.getSubReg(Dst, DstSub);
341 Dst = TRI.getSubReg(Dst, DstSub);
346 return TRI.getSubReg(DstReg, SrcSub) == Dst;
667 UseMI->getOperand(0).getSubReg())
[all...] |
| LiveDebugVariables.cpp | 185 locations[i].getSubReg() == LocMO.getSubReg())
563 if (UI.getOperand().getSubReg() || !UI->isCopy())
794 MO.setSubReg(locations[OldLocNo].getSubReg());
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_3)
[all...] |
| ARMMCInstLower.cpp | 74 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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| Thumb2ITBlockPass.cpp | 113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &&
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| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 631 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
643 getOperand(0).getSubReg() == getOperand(1).getSubReg();
[all...] |
| MachineOperand.h | 262 unsigned getSubReg() const {
326 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
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| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 90 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
91 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
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| MipsSEInstrInfo.cpp | 336 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
351 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
353 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 309 /// getSubReg - Returns the physical register number of sub-register "Index"
312 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 189 if (Src.getSubReg() != Hexagon::subreg_loreg)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMCInstLower.cpp | 157 assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
