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    Searched refs:hasSubClassEq (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 165 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
167 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
169 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
171 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
173 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
192 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
194 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
196 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
200 else if (Mips::FGR64RegClass.hasSubClassEq(RC)
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 449 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
465 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
481 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
486 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
491 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
533 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
567 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
617 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
626 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
635 } else if (PPC::F8RCRegClass.hasSubClassEq(RC))
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 125 return RC != this && hasSubClassEq(RC);
128 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
130 bool hasSubClassEq(const TargetRegisterClass *RC) const {
144 return RC->hasSubClassEq(this);
148 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 773 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
777 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
785 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
793 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
810 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
830 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
852 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
    [all...]
Thumb1RegisterInfo.cpp 51 if (ARM::tGPRRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/X86/
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/CodeGen/
TargetInstrInfoImpl.cpp 274 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 369 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
373 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
377 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 540 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
    [all...]

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