| /external/clang/test/CodeGen/ |
| mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
| mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
|
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 5 typedef int v4i32 __attribute__((ext_vector_type(4))); typedef
50 void print_v4i32(const char *str, v4i32 v) {
76 v4i32 v4i32_shuffle_1(v4i32 a) {
77 v4i32 c2 = a.yzwx;
81 v4i32 v4i32_shuffle_2(v4i32 a) {
82 v4i32 c2 = a.zwxy;
86 v4i32 v4i32_shuffle_3(v4i32 a)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 69 v4i32 = 23, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
188 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
246 case v4i32:
279 case v4i32:
328 case v4i32:
411 if (NumElements == 4) return MVT::v4i32;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 225 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_avar; break;
255 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_asi; break;
285 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_ari; break;
314 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_areg; break;
411 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_avar; break;
442 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_asi; break;
473 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_ari; break;
502 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_areg; break;
|
| NVPTXISelLowering.cpp | 94 addRegisterClass(MVT::v4i32, &NVPTX::V4I32RegsRegClass);
102 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32 , Custom);
113 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32 , Custom);
196 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32 , Custom);
217 // That is why v4i32 or v2i32 are used here.
221 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
223 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
226 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
228 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
[all...] |
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 133 case MVT::v4i32: return "v4i32";
184 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 404 addRegisterClass(MVT::v4i32, &SPU::VECREGRegClass);
701 SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
[all...] |
| SPUISelDAGToDAG.cpp | 120 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
135 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
183 ((vecVT == MVT::v4i32) &&
590 case MVT::v4i32:
654 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
662 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
670 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 79 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
184 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
192 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
277 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
285 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 328 // We promote all non-typed operations to v4i32.
330 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
332 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
370 setOperationAction(ISD::AND , MVT::v4i32, Legal);
371 setOperationAction(ISD::OR , MVT::v4i32, Legal);
372 setOperationAction(ISD::XOR , MVT::v4i32, Legal)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 269 case MVT::v4i32:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 158 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
466 addQRTypeForNEON(MVT::v4i32);
523 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
559 // It is legal to extload from v4i8 to v4i16 or v4i32.
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 81 case MVT::v4i32: return "MVT::v4i32";
|
