/external/v8/src/mips/ |
macro-assembler-mips.cc | 214 Branch(&ok, eq, t8, Operand(zero_reg)); 326 Branch(&done, eq, t8, Operand(zero_reg)); 329 Ret(eq, t8, Operand(zero_reg)); 361 scratch, Operand(zero_reg)); 430 nor(scratch, reg0, zero_reg); 531 Branch(miss, ne, at, Operand(zero_reg)); 755 subu(at, zero_reg, rt.rm()); 779 addiu(rd, zero_reg, j.imm32_); 781 ori(rd, zero_reg, j.imm32_); 962 Subu(at, zero_reg, Operand(1)) [all...] |
builtins-mips.cc | 144 __ mov(scratch3, zero_reg); 221 ne, "array size is unexpectedly 0", array_size, Operand(zero_reg)); 329 __ Branch(&argc_one_or_more, ne, a0, Operand(zero_reg)); 352 __ Branch(¬_empty_array, ne, a2, Operand(zero_reg)); 354 __ mov(a0, zero_reg); // Treat this as a call with argc of zero. 359 __ Branch(call_generic_code, eq, a3, Operand(zero_reg)); 496 t0, Operand(zero_reg)); 532 t0, Operand(zero_reg)); 567 t0, Operand(zero_reg)); 605 __ Branch(&no_arguments, eq, a0, Operand(zero_reg)); [all...] |
code-stubs-mips.cc | 222 __ Assert(eq, message, a3, Operand(zero_reg)); 475 __ subu(at, zero_reg, source_); 491 __ mov(mantissa, zero_reg); 706 __ Branch(&done, eq, int_scratch, Operand(zero_reg)); 712 __ Branch(&skip_sub, ge, dst2, Operand(zero_reg)); 713 __ Subu(int_scratch, zero_reg, int_scratch); 737 __ Branch(&fewer_than_20_useful_bits, lt, scratch2, Operand(zero_reg)); 752 __ mov(dst1, zero_reg); 806 __ Branch(not_int32, ne, except_flag, Operand(zero_reg)); 821 __ Branch(&done, eq, scratch1, Operand(zero_reg)); [all...] |
lithium-codegen-mips.cc | 146 __ Branch(&ok, eq, t1, Operand(zero_reg)); 167 __ Branch(&loop, ne, a0, Operand(zero_reg)); 881 __ Branch(USE_DELAY_SLOT, &positive_dividend, ge, left, Operand(zero_reg)); 882 __ subu(result, zero_reg, left); 885 DeoptimizeIf(eq, instr->environment(), result, Operand(zero_reg)); 888 __ subu(result, zero_reg, result); 898 DeoptimizeIf(eq, instr->environment(), right, Operand(zero_reg)); 901 __ Branch(USE_DELAY_SLOT, &done, ge, left, Operand(zero_reg)); 905 DeoptimizeIf(eq, instr->environment(), result, Operand(zero_reg)); 923 DeoptimizeIf(eq, instr->environment(), right, Operand(zero_reg)); [all...] |
regexp-macro-assembler-mips.cc | 205 BranchOrBacktrack(¬_at_start, eq, a0, Operand(zero_reg)); 218 BranchOrBacktrack(on_not_at_start, eq, a0, Operand(zero_reg)); 302 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); 306 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); 393 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg)); 413 __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); 417 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg)); 566 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); 579 BranchOrBacktrack(on_no_match, ne, a0, Operand(zero_reg)); 644 __ Branch(&stack_limit_hit, le, a0, Operand(zero_reg)); [all...] |
assembler-mips.cc | 116 0, // zero_reg 156 zero_reg, 586 // nop(type) == sll(zero_reg, zero_reg, type); 591 rt == static_cast<uint32_t>(ToNumber(zero_reg)) && 592 rs == static_cast<uint32_t>(ToNumber(zero_reg)) && 1060 beq(zero_reg, zero_reg, offset); 1066 bgezal(zero_reg, offset); 1094 GenInstrImmediate(BGTZ, rs, zero_reg, offset) [all...] |
macro-assembler-mips.h | 172 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \ 173 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT 193 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) { 440 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as 455 // Return <n> if we have a sll zero_reg, zero_reg, n 458 rt == static_cast<uint32_t>(ToNumber(zero_reg)) && 459 rs == static_cast<uint32_t>(ToNumber(zero_reg))); [all...] |
codegen-mips.cc | 370 __ Branch(&check_sequential, eq, at, Operand(zero_reg)); 375 __ Branch(&cons_string, eq, at, Operand(zero_reg)); 408 __ Branch(&external_string, ne, at, Operand(zero_reg)); 424 at, Operand(zero_reg)); 429 __ Branch(call_runtime, ne, at, Operand(zero_reg)); 436 __ Branch(&ascii, ne, at, Operand(zero_reg));
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full-codegen-mips.cc | 62 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy 65 // The marker instruction is effectively a NOP (dest is zero_reg) and will 87 __ Branch(target, eq, at, Operand(zero_reg)); 98 __ Branch(target, ne, at, Operand(zero_reg)); 105 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask); 166 __ Branch(&ok, eq, t1, Operand(zero_reg)); 322 __ mov(v0, zero_reg); 373 __ slt(at, a3, zero_reg); 374 __ beq(at, zero_reg, &ok); 381 __ beq(at, zero_reg, &ok) [all...] |
stub-cache-mips.cc | 146 __ Branch(miss_label, ne, scratch0, Operand(zero_reg)); 601 __ push(zero_reg); 670 __ sw(zero_reg, MemOperand(a1, 3 * kPointerSize)); [all...] |
ic-mips.cc | 94 __ Branch(miss, ne, scratch1, Operand(zero_reg)); 150 __ Branch(miss, ne, at, Operand(zero_reg)); 204 __ Branch(miss, ne, at, Operand(zero_reg)); 280 __ Branch(slow, ne, at, Operand(zero_reg)); 371 __ Branch(index_string, eq, at, Operand(zero_reg)); 378 __ Branch(not_symbol, eq, at, Operand(zero_reg)); 771 __ Branch(slow_case, ne, scratch1, Operand(zero_reg)); [all...] |
lithium-codegen-mips.h | 231 Register src1 = zero_reg, 232 const Operand& src2 = Operand(zero_reg));
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code-stubs-mips.h | 500 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) | 501 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); 507 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) | 508 (zero_reg.code() << kRtShift) | (offset & kImm16Mask)); [all...] |
debug-mips.cc | 99 // nop(DEBUG_BREAK_NOP) - nop(1) is sll(zero_reg, zero_reg, 1) 144 eq, "Unable to encode value as smi", at, Operand(zero_reg));
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deoptimizer-mips.cc | 122 // sltu at, sp, t0 / slt at, a3, zero_reg (in case of count based interrupts) 123 // beq at, zero_reg, ok 134 patcher.masm()->addiu(at, zero_reg, 1); 145 // addiu at, zero_reg, 1 146 // beq at, zero_reg, ok ;; Not changed 171 patcher.masm()->slt(at, a3, zero_reg); 804 __ mov(a3, zero_reg); [all...] |
simulator-mips.h | 145 zero_reg = 0, enumerator in enum:v8::internal::Simulator::Register
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assembler-mips.h | 79 return reg.code() - 2; // zero_reg and 'at' are skipped. 84 return from_code(index + 2); // zero_reg and 'at' are skipped. 134 REGISTER(zero_reg, 0); 666 sll(zero_reg, zero_reg, type, true); 729 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop [all...] |
/external/v8/test/cctest/ |
test-assembler-mips.cc | 139 __ ori(t0, zero_reg, 0); 193 __ addiu(v0, zero_reg, 0x7421); // 0x00007421 577 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); 590 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); 594 __ Addu(t0, zero_reg, Operand(1)); 1176 __ ctc1(zero_reg, FCSR); 1195 __ ctc1(zero_reg, FCSR); \ [all...] |