| /external/webkit/Source/WebKit/chromium/src/ |
| ApplicationCacheHost.cpp | 92 // the usual resource loading pipeline.
|
| /frameworks/av/media/libstagefright/codecs/mp3dec/ |
| SoftMP3.cpp | 271 // decoder have zero delay, which the rest of the pipeline assumes.
|
| /libcore/luni/src/main/java/javax/xml/validation/ |
| TypeInfoProvider.java | 161 * the attribute was originally present in the pipeline, and
|
| /system/core/sh/ |
| eval.c | 482 * Evaluate a pipeline. All the processes in the pipeline are children
483 * of the process creating the pipeline. (This differs from some versions
484 * of the shell, which make the last process in a pipeline the parent
|
| parser.c | 106 STATIC union node *pipeline(void);
225 n1 = pipeline();
235 n2 = pipeline();
247 pipeline(void) function
254 TRACE(("pipeline: entered\n"));
[all...] |
| /external/libvorbis/doc/ |
| 01-introduction.tex | 135 pipeline. Each different component instance of a specific type is
138 instances into a decode pipeline. Componentry arrangement is roughly
143 \captionof{figure}{decoder pipeline configuration}
|
| /external/nist-sip/java/gov/nist/javax/sip/stack/ |
| TCPMessageChannel.java | 592 Pipeline hispipe = null;
593 // Create a pipeline to connect to our message parser.
594 hispipe = new Pipeline(myClientInputStream, sipStack.readTimeout,
|
| TLSMessageChannel.java | 572 Pipeline hispipe = null;
573 // Create a pipeline to connect to our message parser.
574 hispipe = new Pipeline(myClientInputStream, sipStack.readTimeout,
|
| /external/oprofile/events/i386/nehalem/ |
| events | 38 event:0x1E counters:0,1,2,3 um:one minimum:6000 name:INST_QUEUE_WRITE_CYCLES : This event counts the number of cycles during which instructions are written to the instruction queue. Dividing this counter by the number of instructions written to the instruction queue (INST_QUEUE_WRITES) yields the average number of instructions decoded each cycle. If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline.
72 event:0xA7 counters:0,1,2,3 um:one minimum:6000 name:BACLEAR_FORCE_IQ : Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ is also responsible for providing conditional branch prediciton direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target is not found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.
91 event:0xD4 counters:0,1,2,3 um:one minimum:6000 name:SEG_RENAME_STALLS : Counts the number of stall cycles due to the lack of renaming resources for the ES, DS, FS, and GS segment registers. If a segment is renamed but not retired and a second update to the same segment occurs, a stall occurs in the front-end of the pipeline until the renamed segment retires.
|
| /frameworks/av/media/libstagefright/tests/ |
| SurfaceMediaSource_test.cpp | 736 ALOGV("************** Testing the whole pipeline with actual MediaRecorder ***********");
869 ALOGV("************** Testing the whole pipeline with actual Recorder ***********");
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/libexec/gcc/i686-linux/4.4.3/ |
| collect2 | |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/libexec/gcc/i686-linux/4.6.x-google/ |
| collect2 | |
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.6/libexec/gcc/mipsel-linux-android/4.6/ |
| collect2 | |
| /prebuilts/gcc/linux-x86/x86/i686-linux-android-4.6/libexec/gcc/i686-linux-android/4.6/ |
| collect2 | |
| /external/oprofile/events/ia64/itanium2/ |
| events | 65 event:0x67 counters:0,1,2,3 um:l1i_prefetch_stall minimum:5000 name:L1I_PREFETCH_STALL : Why prefetch pipeline is stalled?
79 #event:0xc3 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
81 #event:0xc5 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
88 event:0xc3 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
92 event:0xc5 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
|
| /external/mksh/src/ |
| mksh.1 | 496 The exit status of a pipeline is that of its last command.
497 All commands of a pipeline are executed in separate subshells;
504 A pipeline may be prefixed by the
506 reserved word which causes the exit status of the pipeline to be logically
855 .Op Ar pipeline
[all...] |
| /external/openssl/crypto/rc4/asm/ |
| rc4-ia64.pl | 49 # code below has the following pipeline diagram:
126 # particular, note that the first stage of the pipeline is
402 We must perform the first phase of the pipeline explicitly since
|
| /frameworks/support/v4/java/android/support/v4/view/ |
| ViewCompat.java | 74 * rendering pipeline, even if hardware acceleration is enabled.</p>
82 * accelerated pipeline. It can also be used to cache a complex view tree
98 * rendering pipeline, but only if hardware acceleration is turned on for the
[all...] |
| /external/llvm/docs/CommandGuide/ |
| llvm-bcanalyzer.rst | 25 from standard input. This is useful for combining the tool into a pipeline.
|
| /external/llvm/docs/HistoricalNotes/ |
| 2001-02-09-AdveCommentsResponse.txt | 145 > Other classes of instructions that are valuable for pipeline
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 135 /// pipeline flush.
|
| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.cpp | 117 // Pass Pipeline Configuration
|
| /external/openssl/crypto/sha/asm/ |
| sha1-s390x.pl | 21 # instructions to favour dual-issue z10 pipeline. On z10 hardware is
|
| sha256-armv4.pl | 18 # Rescheduling for dual-issue pipeline resulted in 22% improvement on
|
| /external/webkit/Source/ThirdParty/ANGLE/src/libEGL/ |
| Surface.cpp | 188 // Disable all pipeline operations
|
