| /external/oprofile/events/ppc64/power5+/ |
| event_mappings | 330 #Group 41 pm_ic_miss, ICache misses
338 #Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
362 #Group 45 pm_L1_tlbmiss, L1 load and TLB misses
370 #Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
378 #Group 47 pm_L1_slbmiss, L1 load and SLB misses
394 #Group 49 pm_dtlbmiss, Data TLB misses
402 #Group 50 pm_dtlb, Data TLB references and misses
410 #Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
[all...] |
| /external/oprofile/events/i386/p6_mobile/ |
| events | 10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
|
| /external/oprofile/events/i386/pii/ |
| events | 10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
|
| /external/oprofile/events/i386/piii/ |
| events | 10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
|
| /frameworks/base/core/tests/coretests/src/android/util/ |
| LruCacheTest.java | 146 assertEquals("LruCache[maxSize=3,hits=0,misses=0,hitRate=0%]", cache.toString());
159 assertEquals("LruCache[maxSize=3,hits=3,misses=2,hitRate=60%]", cache.toString());
|
| /dalvik/vm/compiler/ |
| Compiler.h | 40 /* Rechain after this many misses - shared globally and has to be positive */
|
| /external/chromium/chrome/browser/safe_browsing/ |
| safe_browsing_store.cc | 146 // Collect the misses which are not present in |add_prefixes|.
|
| /external/oprofile/events/i386/p4/ |
| unit_masks | 44 0x400 writeback lookup from DAC misses 2nd level cache
|
| /external/qemu/slirp/ |
| tcp_var.h | 221 u_long tcps_socachemiss; /* tcp_last_so misses */
|
| /external/v8/test/mjsunit/ |
| delete.js | 161 // when the dictionary probe misses.
|
| /external/valgrind/main/cachegrind/ |
| cg_sim.c | 37 - one block hits, the other misses --> one miss
|
| /external/oprofile/events/i386/core_2/ |
| events | 51 event:0x48 counters:0,1 um:zero minimum:500 name:L1D_PEND_MISS : Total number of outstanding L1 data cache misses at any cycle
82 event:0x81 counters:0,1 um:zero minimum:500 name:L1I_MISSES : number of instruction fetch misses
83 event:0x82 counters:0,1 um:itlb_miss minimum:500 name:ITLB : number of ITLB misses
|
| /external/oprofile/events/i386/nehalem/ |
| events | 27 event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB
50 event:0x49 counters:0,1,2,3 um:dtlb_misses minimum:6000 name:DTLB_MISSES : Counts the number of misses in the STLB
66 event:0x85 counters:0,1,2,3 um:itlb_misses minimum:6000 name:ITLB_MISSES : Counts the number of ITLB misses in various variants
|
| /external/oprofile/events/ppc64/power7/ |
| events | 101 #Group 11 pm_slb_miss, SLB Misses
103 event:0X00B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP11 : (Group 11 pm_slb_miss) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
105 event:0X00B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP11 : (Group 11 pm_slb_miss) Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.
109 #Group 12 pm_tlb_miss, TLB Misses
111 event:0X00C1 counters:1 um:zero minimum:1000 name:PM_TLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Total of Data TLB mises + Instruction TLB misses
112 event:0X00C2 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Data TLB misses, all page sizes.
117 #Group 13 pm_dtlb_miss, DTLB Misses
125 #Group 14 pm_derat_miss1, DERAT misses
133 #Group 15 pm_derat_miss2, DERAT misses
141 #Group 16 pm_misc_miss1, Misses
[all...] |
| /external/oprofile/events/ppc64/power5/ |
| event_mappings | 322 #Group 40 pm_ic_miss, ICache misses
330 #Group 41 pm_branch_miss, Branch mispredict, TLB and SLB misses
354 #Group 44 pm_L1_tlbmiss, L1 load and TLB misses
362 #Group 45 pm_L1_DERAT_miss, L1 store and DERAT misses
370 #Group 46 pm_L1_slbmiss, L1 load and SLB misses
378 #Group 47 pm_L1_dtlbmiss_4K, L1 load references and 4K Data TLB references and misses
386 #Group 48 pm_L1_dtlbmiss_16M, L1 store references and 16M Data TLB references and misses
[all...] |
| /external/valgrind/main/callgrind/ |
| sim.c | 42 - one block hits, the other misses --> one miss
[all...] |
| /external/antlr/antlr-3.4/runtime/Ruby/lib/antlr3/ |
| profile.rb | 164 report << "| %-66s | %7i |\n" % [ "Cache Misses", memoization_cache_misses ]
|
| /external/llvm/test/Analysis/ScalarEvolution/ |
| scev-aa.ll | 4 ; At the time of this writing, -basicaa misses the example of the form
|
| /external/llvm/test/CodeGen/X86/ |
| lsr-delayed-fold.ll | 3 ; ScalarEvolution misses an opportunity to fold ((trunc x) + (trunc -x) + y),
|
| /external/llvm/test/Transforms/SimplifyCFG/ |
| indirectbr.ll | 35 ; better if it removed the branch altogether, but simplifycfdg currently misses
|
| /external/oprofile/events/i386/atom/ |
| events | 25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
|
| /external/oprofile/events/x86-64/family11h/ |
| unit_masks | 183 0x02 Data cache misses by locked instructions
|
| /external/oprofile/events/x86-64/hammer/ |
| unit_masks | 176 0x02 Data cache misses by locked instructions
|
| /external/qemu/slirp-android/ |
| tcp_var.h | 225 u_long tcps_socachemiss; /* tcp_last_so misses */
|
| /frameworks/base/core/java/android/util/ |
| LruCache.java | 378 return String.format("LruCache[maxSize=%d,hits=%d,misses=%d,hitRate=%d%%]",
|
