/system/core/libpixelflinger/codeflinger/ |
GGLAssembler.cpp | 433 ADD(AL, 0, Rs, Rs, reg_imm(parts.count.reg, LSR, 16)); 556 MOV(AL, 0, fragment.reg, reg_imm(incoming.reg, LSR, incoming.l)); 576 reg_imm(mAlphaSource.reg, LSR, shift)); 585 reg_imm(fragment.reg, LSR, shift)); 705 if (shift) CMP(AL, fragment.reg, reg_imm(ref, LSR, shift)); 769 SUB(AL, 0, zbase, zbase, reg_imm(parts.count.reg, LSR, 15)); 774 CMP(AL, depth, reg_imm(z, LSR, 16)); 782 MOV(AL, 0, depth, reg_imm(z, LSR, 16)); [all...] |
ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR
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MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break; 509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; 541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; [all...] |
/external/tremolo/Tremolo/ |
bitwiseARM.s | 57 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord) 81 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits 155 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data 248 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord) 273 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits 395 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data
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floor1ARM.s | 59 MOVS r6, r6, LSR #15
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mdctLARM.s | 264 MOV r0, r0, LSR #2 @ n >>= 2 420 MOV r0, r0, LSR #1 @ r0 = points>>i = POINTS 421 MOV r2, r14,LSR #2 @ r2 = (1<<i)-j (j=0) 993 LDRB r7, [r6, r4, LSR #6] 999 ADD r9, r1, r7, LSR r3 @ r9 = xx = x + (b>>shift) 1022 ADDGE r5, r5, r2, LSR #1 @ (step>>1) 1114 ADDGE r5, r5, r2, LSR #1 @ (step>>1)
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
omxVCM4P2_PredictReconCoefIntra_s.s | 185 LSR tempPred,tempPred,#15 ;// tempped=pPredBufRow(Col)[0]/dcScaler 186 LSR temp3,temp3,#1 ;// temp3=round(dcScaler/2)
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
h264bsd_interpolate_hor_quarter.s | 264 SBC mb, mb, tmp3, LSR #20 ;// -(partWidth-1)-1 265 SBC ref, ref, tmp3, LSR #20 ;// -(partWidth-1)-1
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h264bsd_interpolate_mid_hor.s | 156 SBC ref, ref, tmp3, LSR #16 ;// -(partWidth-1)-1
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/external/sonivox/arm-hybrid-22k/lib_src/ |
ARM-E_interpolate_loop_gnu.s | 116 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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ARM-E_interpolate_noloop_gnu.s | 108 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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/external/sonivox/arm-wt-22k/lib_src/ |
ARM-E_interpolate_loop_gnu.s | 116 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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ARM-E_interpolate_noloop_gnu.s | 108 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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/external/v8/src/arm/ |
debug-arm.cc | 175 __ mov(reg, Operand(reg, LSR, kSmiTagSize));
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stub-cache-arm.cc | 237 __ mov(scratch, Operand(scratch, LSR, kHeapObjectTagSize)); 257 __ sub(scratch, scratch, Operand(name, LSR, kHeapObjectTagSize)); [all...] |
constants-arm.h | 288 LSR = 1 << 5, // Logical shift right.
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macro-assembler-arm.cc | 303 mov(dst, Operand(dst, LSR, lsb), LeaveCC, cond); [all...] |
code-stubs-arm.cc | 513 Operand(source_, LSR, 32 - HeapNumber::kMantissaBitsInTopWord)); 729 __ orr(dst2, dst2, Operand(int_scratch, LSR, scratch2)); [all...] |
disasm-arm.cc | 204 "lsl", "lsr", "asr", "ror" 227 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) { [all...] |
/external/v8/test/cctest/ |
test-disasm-arm.cc | 136 COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)), 137 "e06760ab rsb r6, r7, fp, lsr #1"); 138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC), 139 "e077602b rsbs r6, r7, fp, lsr #32"); 140 COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl), 141 "50676fab rsbpl r6, r7, fp, lsr #31"); 201 COMPARE(cmp(r7, Operand(r8, LSR, 3), gt), 202 "c15701a8 cmpgt r7, r8, lsr #3");
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm/ |
h264bsdWriteMacroblock.s | 103 LSR cwidth, width, #1
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/ |
h264bsdWriteMacroblock.S | 105 LSR cwidth, width, #1
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.s | 158 MOVEQ filt, filt, LSR #16
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omxVCM4P10_PredictIntra_16x16_s.s | 224 ADD tVal2, tVal2, tVal2, LSR #16 ;// sum(pSrcAbove[0] to pSrcAbove[15])
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/external/llvm/test/MC/ARM/ |
basic-thumb-instructions.s | 348 @ LSR (immediate) 364 @ LSR (register)
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