| /external/tremolo/Tremolo/ |
| mdctARM.s | 261 MOV r0, r0, LSR #2 @ n >>= 2
437 MOV r0, r0, LSR #1 @ r0 = points>>i = POINTS
438 MOV r2, r14,LSR #2 @ r2 = (1<<i)-j (j=0)
1004 LDRB r7, [r6, r4, LSR #6]
1010 MOV r7, r7, LSR r3
[all...] |
| /external/v8/src/arm/ |
| regexp-macro-assembler-arm.cc | 730 __ mov(r1, Operand(r1, LSR, 1));
[all...] |
| simulator-arm.cc | [all...] |
| lithium-codegen-arm.cc | [all...] |
| builtins-arm.cc | [all...] |
| full-codegen-arm.cc | [all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intARM.stdout.exp | 111 LSR
112 lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
113 lsr r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000
114 lsr r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000
115 lsr r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000
116 lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000
117 lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000
118 lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000
119 lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000
120 lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000
[all...] |
| /external/openssl/crypto/aes/asm/ |
| bsaes-x86_64.pl | 667 movdqa 0x30($const),@t[0] # .LSR
793 movdqa 0x30($const), @XMM[8] # .LSR
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 49 adc.w r0, r1, r3, lsr #31
59 @ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70]
118 adds.w r0, r3, r6, lsr #25
126 @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60]
164 ands.w r4, r5, r2, lsr #20
170 @ CHECK: ands.w r4, r5, r2, lsr #20 @ encoding: [0x15,0xea,0x12,0x54]
260 bic r8, r4, r1, lsr #11
261 bic r7, r5, r7, lsr #15
269 bic r6, r3, lsr #12
270 bic r7, r4, lsr #
[all...] |
| basic-arm-instructions.s | 52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
63 adc r6, r7, r8, lsr r9
72 adc r4, r5, lsr #1
73 adc r4, r5, lsr #31
74 adc r4, r5, lsr #32
82 adc r6, r7, lsr r9
91 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
92 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0
[all...] |
