| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.h | 32 MachineBasicBlock::iterator MI,
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| MipsRegisterInfo.cpp | 157 MachineInstr &MI = *II;
158 MachineFunction &MF = *MI.getParent()->getParent();
161 while (!MI.getOperand(i).isFI()) {
163 assert(i < MI.getNumOperands() &&
168 errs() << "<--------->\n" << MI);
170 int FrameIndex = MI.getOperand(i).getIndex();
178 eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
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| /external/clang/include/clang/Lex/ |
| PPCallbacks.h | 166 virtual void MacroExpands(const Token &MacroNameTok, const MacroInfo* MI,
171 virtual void MacroDefined(const Token &MacroNameTok, const MacroInfo *MI) {
176 /// MI is released immediately following this callback.
177 virtual void MacroUndefined(const Token &MacroNameTok, const MacroInfo *MI) {
318 virtual void MacroExpands(const Token &MacroNameTok, const MacroInfo* MI,
320 First->MacroExpands(MacroNameTok, MI, Range);
321 Second->MacroExpands(MacroNameTok, MI, Range);
324 virtual void MacroDefined(const Token &MacroNameTok, const MacroInfo *MI) {
325 First->MacroDefined(MacroNameTok, MI);
326 Second->MacroDefined(MacroNameTok, MI);
[all...] |
| TokenLexer.h | 101 TokenLexer(Token &Tok, SourceLocation ILEnd, MacroInfo *MI,
104 Init(Tok, ILEnd, MI, ActualArgs);
111 void Init(Token &Tok, SourceLocation ILEnd, MacroInfo *MI,
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| /external/llvm/include/llvm/ADT/ |
| EquivalenceClasses.h | 44 /// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I);
45 /// MI != EC.member_end(); ++MI) // Loop over members in this set.
46 /// cerr << *MI << " "; // Print member.
124 member_iterator MI = RHS.member_begin(I);
125 member_iterator LeaderIt = member_begin(insert(*MI));
126 for (++MI; MI != member_end(); ++MI)
127 unionSets(LeaderIt, member_begin(insert(*MI)));
[all...] |
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.h | 90 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
96 void PrescanInstruction(MachineInstr *MI);
97 void ScanInstruction(MachineInstr *MI, unsigned Count);
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| ExpandISelPseudos.cpp | 55 MachineInstr *MI = MBBI++;
57 // If MI is a pseudo, expand it.
58 if (MI->usesCustomInsertionHook()) {
61 TLI->EmitInstrWithCustomInserter(MI, MBB);
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| AggressiveAntiDepBreaker.cpp | 206 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
211 GetPassthruRegs(MI, PassthruRegs);
212 PrescanInstruction(MI, Count, PassthruRegs);
213 ScanInstruction(MI, Count);
216 DEBUG(MI->dump());
240 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
252 Op = MI->findRegisterUseOperand(Reg, true);
254 Op = MI->findRegisterDefOperand(Reg);
259 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
261 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
[all...] |
| RegAllocBase.cpp | 111 MachineInstr *MI;
113 (MI = I.skipInstruction());)
114 if (MI->isInlineAsm())
116 if (MI)
117 MI->emitError(Msg);
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| TailDuplication.cpp | 86 void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
92 void DuplicateInstruction(MachineInstr *MI,
152 MachineBasicBlock::iterator MI = MBB->begin();
153 while (MI != MBB->end()) {
154 if (!MI->isPHI())
160 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
161 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
168 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
175 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
176 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB()
[all...] |
| VirtRegMap.cpp | 265 MachineInstr *MI = MII;
268 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
269 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
319 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
322 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
325 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
327 DEBUG(dbgs() << "> " << *MI);
330 if (MI->isIdentityCopy()) {
332 if (MI->getNumOperands() == 2) {
335 Indexes->removeMachineInstrFromMaps(MI);
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CheckObjCInstMethSignature.cpp | 113 MapTy::iterator MI = IMeths.find(S);
115 if (MI == IMeths.end() || MI->second == 0)
119 ObjCMethodDecl *MethDerived = MI->second;
120 MI->second = 0;
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| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 109 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
110 OutMI.setOpcode(MI->getOpcode());
112 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
113 const MachineOperand &MO = MI->getOperand(i);
118 MI->dump();
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| /external/clang/lib/Lex/ |
| PPMacroExpansion.cpp | 50 void Preprocessor::setMacroInfo(IdentifierInfo *II, MacroInfo *MI,
52 assert(MI && "MacroInfo should be non-zero!");
53 MI->setPreviousDefinition(Macros[II]);
54 Macros[II] = MI;
76 MacroInfo *MI = PP.AllocateMacroInfo(SourceLocation());
77 MI->setIsBuiltinMacro();
78 PP.setMacroInfo(Id, MI);
114 /// isTrivialSingleTokenExpansion - Return true if MI, which has a single token
116 static bool isTrivialSingleTokenExpansion(const MacroInfo *MI,
119 IdentifierInfo *II = MI->getReplacementToken(0).getIdentifierInfo()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 123 static bool hasYmmReg(MachineInstr *MI) {
124 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
125 const MachineOperand &MO = MI->getOperand(i);
219 MachineInstr *MI = I;
221 bool isControlFlow = MI->isCall() || MI->isReturn();
227 if (hasYmmReg(MI)) {
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| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 235 MachineInstr *MI = I;
236 DebugLoc dl = MI->getDebugLoc();
283 MachineInstr &MI = *II;
285 MachineBasicBlock &MBB = *MI.getParent();
292 DebugLoc dl = MI.getDebugLoc();
348 .addReg(MI.getOperand(1).getReg());
353 .addReg(MI.getOperand(1).getReg());
355 if (!MI.getOperand(1).isKill())
356 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
361 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 57 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
58 int Opcode = MI->getOpcode();
61 if ((MI->getOperand(1).isFI()) && // is a stack slot
62 (MI->getOperand(2).isImm()) && // the imm is zero
63 (isZeroImm(MI->getOperand(2))))
65 FrameIndex = MI->getOperand(1).getIndex();
66 return MI->getOperand(0).getReg();
78 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
80 int Opcode = MI->getOpcode();
83 if ((MI->getOperand(1).isFI()) && // is a stack slo
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 206 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
225 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
240 MI->addOperand(MachineOperand::CreateReg(Reg, true));
252 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
293 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
305 const MCInstrDesc &MCID = MI->getDesc();
317 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
339 unsigned Idx = MI->getNumOperands();
341 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 310 // If starting offset isn't zero, insert a MI to materialize a new base.
515 static bool definesCPSR(MachineInstr *MI) {
516 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
517 const MachineOperand &MO = MI->getOperand(i);
529 static bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
533 if (!MI)
537 switch (MI->getOpcode()) {
551 unsigned Scale = (MI->getOpcode() == ARM::tSUBspi) ? 4 : 1; // FIXME
552 if (!(MI->getOperand(0).getReg() == Base &&
553 MI->getOperand(1).getReg() == Base &
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 72 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 switch (MI->getOpcode()) {
85 const MachineOperand MOp1 = MI->getOperand(1);
86 const MachineOperand MOp2 = MI->getOperand(2);
89 return MI->getOperand(0).getReg();
98 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
100 switch (MI->getOpcode()) {
112 const MachineOperand MOp1 = MI->getOperand(1);
113 const MachineOperand MOp2 = MI->getOperand(2);
116 return MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 40 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
42 if (MI->getOpcode() == SP::LDri ||
43 MI->getOpcode() == SP::LDFri ||
44 MI->getOpcode() == SP::LDDFri) {
45 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
46 MI->getOperand(2).getImm() == 0) {
47 FrameIndex = MI->getOperand(1).getIndex();
48 return MI->getOperand(0).getReg();
59 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
[all...] |
| DelaySlotFiller.cpp | 64 void insertCallUses(MachineBasicBlock::iterator MI,
67 void insertDefsUses(MachineBasicBlock::iterator MI,
233 void Filler::insertCallUses(MachineBasicBlock::iterator MI,
237 switch(MI->getOpcode()) {
242 assert(MI->getNumOperands() >= 2);
243 const MachineOperand &Reg = MI->getOperand(0);
248 const MachineOperand &RegOrImm = MI->getOperand(1);
258 //Insert Defs and Uses of MI into the sets RegDefs and RegUses.
259 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
263 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalAnalysis.h | 83 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
84 /// unsigned OpNum = findRegMaskOperand(MI);
85 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
216 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
217 return Indexes->insertMachineInstrInMaps(MI);
220 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
221 Indexes->removeMachineInstrFromMaps(MI);
224 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
225 Indexes->replaceMachineInstrInMaps(MI, NewMI);
258 /// instruction 'mi' has been moved within a basic block. This will updat
[all...] |
| ScheduleDAGInstrs.h | 74 const MachineInstr *MI = I;
75 if (MI->isDebugValue())
77 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
78 const MachineOperand &MO = MI->getOperand(i);
263 SUnit *newSUnit(MachineInstr *MI);
265 /// getSUnit - Return an existing SUnit for this MI, or NULL.
266 SUnit *getSUnit(MachineInstr *MI) const;
328 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
332 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
339 /// getSUnit - Return an existing SUnit for this MI, or NULL
[all...] |
