/external/kernel-headers/original/asm-x86/ |
ptrace-abi.h | 35 #define R11 48 52 #define ARGOFFSET R11
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
ptrace-abi.h | 35 #define R11 48 52 #define ARGOFFSET R11
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
ptrace-abi.h | 35 #define R11 48 52 #define ARGOFFSET R11
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
ptrace-abi.h | 35 #define R11 48 52 #define ARGOFFSET R11
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/prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/ |
ptrace-abi.h | 46 #define R11 48 62 #define ARGOFFSET R11
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/prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/ |
ptrace-abi.h | 46 #define R11 48 62 #define ARGOFFSET R11
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/prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/ |
ptrace-abi.h | 46 #define R11 48 62 #define ARGOFFSET R11
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/prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/ |
ptrace-abi.h | 46 #define R11 48 62 #define ARGOFFSET R11
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/prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/ |
ptrace-abi.h | 46 #define R11 48 62 #define ARGOFFSET R11
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
reg.h | 34 # define R11 6
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
reg.h | 34 # define R11 6
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
reg.h | 34 # define R11 6
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/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired. 37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
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/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11: 56 case R8: case R9: case R10: case R11:
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ARMBaseRegisterInfo.cpp | 59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 126 case ARM::R11: 320 ARM::R9, ARM::R11 323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 332 ARM::R9, ARM::R11 335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 340 // FP is R11, R9 is available. 356 ARM::R11 359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 368 ARM::R11 [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
PPCBaseInfo.h | 42 case R11: case X11: case F11: case V11: case CR2UN: return 11;
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/external/llvm/lib/Transforms/InstCombine/ |
InstCombineAndOrXor.cpp | 575 Value *R11,*R12; 577 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) { 578 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { 579 A = R11; D = R12; 581 A = R12; D = R11; 586 } else if (match(R1, m_And(m_Value(R11), m_Value(R12)))) { 587 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) [all...] |
/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
MBlazeBaseInfo.h | 116 case MBlaze::R11 : return 11; 180 case 11 : return MBlaze::R11;
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/external/llvm/lib/Target/MBlaze/ |
MBlazeFrameLowering.cpp | 247 // Build the prologue SWI for R3 - R12 if needed. Note that R11 must 250 if (!MRI.isPhysRegUsed(r) && !(isIntr && r == MBlaze::R11)) continue; 272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11) 274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11) 277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11) 280 .addReg(MBlaze::R11);
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/external/llvm/lib/Target/X86/ |
X86RegisterInfo.cpp | 114 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 345 X86::R8, X86::R9, X86::R10, X86::R11, 634 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 671 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 707 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 759 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 760 return X86::R11;
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/external/valgrind/main/coregrind/m_sigframe/ |
sigframe-arm-linux.c | 149 SC2(fp,R11); 323 REST(fp,R11);
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/external/llvm/lib/Target/X86/Disassembler/ |
X86DisassemblerDecoder.h | 172 ENTRY(R11) \ 190 ENTRY(R11) \
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/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
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/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 457 // we use R11, which we know cannot be used in the prolog/epilog. This is 459 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 461 .addReg(PPC::R11, 623 PPC::R11), FrameIdx)); 624 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 663 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
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/external/valgrind/main/VEX/auxprogs/ |
genoffsets.c | 111 GENOFFSET(AMD64,amd64,R11);
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