| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 81 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
83 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
85 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
86 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
135 bool isScalarFPTypeInSSEReg(EVT VT) const {
136 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
137 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
140 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
150 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
156 VT = evt.getSimpleVT()
[all...] |
| X86ISelLowering.h | 493 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
514 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
532 virtual EVT getSetCCResultType(EVT VT) const;
579 EVT VT) const;
628 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
635 EVT VT) const;
642 EVT VT) const;
647 virtual bool ShouldShrinkFPConstant(EVT VT) const {
651 return !X86ScalarSSEf64 || VT == MVT::f80;
660 bool isScalarFPTypeInSSEReg(EVT VT) const
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 269 virtual EVT getSetCCResultType(EVT VT) const;
281 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
285 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
296 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
344 EVT VT) const;
361 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
374 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
380 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
387 findRepresentativeClass(EVT VT) const;
402 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
[all...] |
| ARMISelDAGToDAG.cpp | 269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 105 EVT getSetCCResultType(EVT VT) const;
168 EVT VT) const;
175 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| MBlazeISelDAGToDAG.cpp | 211 EVT VT = Node->getValueType(0);
212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 79 bool isTypeSupportedInIntrinsic(MVT VT) const;
94 virtual EVT getSetCCResultType(EVT VT) const {
100 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 255 EVT VT = N.getValueType();
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
307 EVT VT = LD->getMemoryVT();
309 switch (VT.getSimpleVT().SimpleTy) {
334 MVT VT = LD->getMemoryVT().getSimpleVT();
337 switch (VT.SimpleTy) {
349 VT, MVT::i16, MVT::Other,
363 MVT VT = LD->getMemoryVT().getSimpleVT();
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
370 VT, MVT::i16, MVT::Other
[all...] |
| MSP430ISelLowering.cpp | 222 EVT VT) const {
228 if (VT == MVT::i8)
235 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
594 EVT VT = Op.getValueType();
603 VT, N->getOperand(0), N->getOperand(1));
606 VT, N->getOperand(0), N->getOperand(1));
609 VT, N->getOperand(0), N->getOperand(1));
622 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
628 dl, VT, Victim);
817 EVT VT = Op.getValueType()
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 349 static const EVT *getValueTypeList(EVT VT);
677 static SDVTList getSDVTList(EVT VT) {
678 SDVTList Ret = { getValueTypeList(VT), 1 };
894 // MemoryVT - VT of in-memory value.
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 155 DeclsTy *VT = new DeclsTy();
156 VT->push_back(OldD);
157 Data = VT;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 128 virtual EVT getSetCCResultType(EVT VT) const {
139 EVT VT) const;
150 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| HexagonInstrInfo.h | 108 unsigned createVR(MachineFunction* MF, MVT VT) const;
147 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 29 EVT VT;
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
320 // add/sub are legal for all supported vector VT's.
321 setOperationAction(ISD::ADD , VT, Legal);
322 setOperationAction(ISD::SUB , VT, Legal);
325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
329 setOperationAction(ISD::AND , VT, Promote);
330 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
331 setOperationAction(ISD::OR , VT, Promote);
332 AddPromotedToType (ISD::OR , VT, MVT::v4i32)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 284 EVT VT = N->getValueType(0);
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
564 EVT VT = N->getValueType(0);
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
605 // Truncate to NVT instead of VT
695 EVT VT = N->getValueType(0);
698 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
699 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| ScheduleDAGRRList.cpp | 271 EVT VT = RegDefPos.GetValue();
275 if (VT == MVT::Untyped) {
295 RegClass = TLI->getRepRegClassFor(VT)->getID();
296 Cost = TLI->getRepRegClassCostFor(VT);
[all...] |
| LegalizeFloatTypes.cpp | 28 static RTLIB::Libcall GetFPLibCall(EVT VT,
34 VT == MVT::f32 ? Call_F32 :
35 VT == MVT::f64 ? Call_F64 :
36 VT == MVT::f80 ? Call_F80 :
37 VT == MVT::ppcf128 ? Call_PPCF128 :
474 EVT VT = N->getValueType(0);
475 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
499 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL));
525 EVT VT = N->getValueType(0);
526 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 772 MVT::SimpleValueType VT;
774 EmitIntegerMatcher(int64_t val, MVT::SimpleValueType vt)
775 : Matcher(EmitInteger), Val(val), VT(vt) {}
778 MVT::SimpleValueType getVT() const { return VT; }
788 cast<EmitIntegerMatcher>(M)->VT == VT;
790 virtual unsigned getHashImpl() const { return (Val << 4) | VT; }
797 MVT::SimpleValueType VT;
799 EmitStringIntegerMatcher(const std::string &val, MVT::SimpleValueType vt)
[all...] |
| IntrinsicEmitter.cpp | 247 static void EncodeFixedValueType(MVT::SimpleValueType VT,
249 if (EVT(VT).isInteger()) {
250 unsigned BitWidth = EVT(VT).getSizeInBits();
261 switch (VT) {
291 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT"));
294 switch (VT) {
328 if (EVT(VT).isVector()) {
329 EVT VVT = VT;
343 EncodeFixedValueType(VT, Sig)
[all...] |
| FastISelEmitter.cpp | 160 OS << "VT == "
175 MVT::SimpleValueType VT,
218 //if (Op->getType(0) != VT)
245 if (Op->getType(0) != VT)
495 MVT::SimpleValueType VT = RetVT;
498 VT = InstPatNode->getChild(0)->getType(0);
507 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
552 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
556 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
601 MVT::SimpleValueType VT = TI->first
[all...] |
| /external/guava/guava/src/com/google/common/base/ |
| Ascii.java | 167 public static final byte VT = 11;
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 106 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
116 EVT getSetCCResultType(EVT VT) const;
187 EVT VT) const;
208 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 109 virtual EVT getSetCCResultType(EVT VT) const;
140 EVT VT) const;
|
