/external/llvm/lib/Target/Sparc/ |
FPMover.cpp | 90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || 91 MI->getOpcode() == SP::FpNEGD) { 95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { 106 if (MI->getOpcode() == SP::FpMOVD) 108 else if (MI->getOpcode() == SP::FpNEGD) 110 else if (MI->getOpcode() == SP::FpABSD)
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/external/llvm/include/llvm/CodeGen/ |
SelectionDAGNodes.h | 140 inline unsigned getOpcode() const; 359 /// getOpcode - Return the SelectionDAG opcode value for this node. For 363 unsigned getOpcode() const { return (unsigned short)NodeType; } 774 inline unsigned SDValue::getOpcode() const { 775 return Node->getOpcode(); [all...] |
MachineInstr.h | 256 /// getOpcode - Returns the opcode of this MachineInstr. 258 int getOpcode() const { return MCID->Opcode; } 597 return getOpcode() == TargetOpcode::PROLOG_LABEL || 598 getOpcode() == TargetOpcode::EH_LABEL || 599 getOpcode() == TargetOpcode::GC_LABEL; 603 return getOpcode() == TargetOpcode::PROLOG_LABEL; 605 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 606 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 607 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 609 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonSplitTFRCondSets.cpp | 85 switch(MI->getOpcode()) { 93 if (MI->getOpcode() == Hexagon::TFR_condset_rr || 94 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { 98 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { 129 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { 134 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { 150 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { 155 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { 178 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) { 187 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) [all...] |
HexagonCFGOptimizer.cpp | 69 switch(MI->getOpcode()) { 106 int Opc = MI->getOpcode(); 158 if ((MI->getOpcode() == Hexagon::JMP_c) || 159 (MI->getOpcode() == Hexagon::JMP_cNot)) { 171 IsUnconditionalJump(LayoutSucc->front().getOpcode())) { 178 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
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/external/llvm/lib/Transforms/InstCombine/ |
InstCombineShifts.cpp | 106 switch (I->getOpcode()) { 201 switch (I->getOpcode()) { 314 bool isLeftShift = I.getOpcode() == Instruction::Shl; 319 if (I.getOpcode() != Instruction::AShr && 337 if (I.getOpcode() != Instruction::AShr) 346 if (BO->getOpcode() == Instruction::Mul && isLeftShift) 372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); 386 if (I.getOpcode() == Instruction::Shl) 389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); 408 switch (Op0BO->getOpcode()) { [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode(); 80 int Opcode = MI->getOpcode(); 209 if (IsBRU(LastInst->getOpcode())) { 214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 235 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 241 && IsBRU(LastInst->getOpcode())) { 253 if (IsBRU(SecondLastInst->getOpcode()) && 254 IsBRU(LastInst->getOpcode())) { 263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { [all...] |
XCoreISelDAGToDAG.cpp | 99 if (Addr.getOpcode() == ISD::ADD) { 115 if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) { 120 if (Addr.getOpcode() == ISD::ADD) { 122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) 136 if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) { 141 if (Addr.getOpcode() == ISD::ADD) { 143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) 157 switch (N->getOpcode()) { 242 if (Chain->getOpcode() != ISD::TokenFactor) 265 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCBranchSelector.cpp | 106 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) { 143 if (I->getOpcode() == PPC::BCC) { 154 } else if (I->getOpcode() == PPC::BDNZ) { 156 } else if (I->getOpcode() == PPC::BDNZ8) { 158 } else if (I->getOpcode() == PPC::BDZ) { 160 } else if (I->getOpcode() == PPC::BDZ8) {
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/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode(); 59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 60 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
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/external/llvm/lib/Target/MBlaze/ |
MBlazeInstrInfo.cpp | 45 if (MI->getOpcode() == MBlaze::LWI) { 64 if (MI->getOpcode() == MBlaze::SWI) { 137 unsigned LastOpc = LastInst->getOpcode(); 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 162 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) && 163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { 165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); 173 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) && 174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { 223 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) & [all...] |
/dalvik/dexgen/src/com/android/dexgen/dex/code/ |
SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
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TargetInsn.java | 61 return new TargetInsn(getOpcode(), getPosition(), registers, target); 75 Dop opcode = getOpcode().getOppositeTest();
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/dalvik/dx/src/com/android/dx/dex/code/ |
SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
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/dalvik/dx/src/com/android/dx/io/instructions/ |
OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
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RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
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TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
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/dalvik/dx/src/com/android/dx/merge/ |
InstructionTransformer.java | 70 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO); 80 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO); 90 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO); 100 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
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/external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
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/external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
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RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
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TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
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/frameworks/compile/libbcc/lib/AndroidBitcode/ |
ABCExpandVAArgPass.cpp | 37 if (inst->getOpcode() == llvm::Instruction::VAArg) {
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/dalvik/dexgen/src/com/android/dexgen/rop/code/ |
FillArrayDataInsn.java | 103 return new FillArrayDataInsn(getOpcode(), getPosition(), 113 return new FillArrayDataInsn(getOpcode(), getPosition(),
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PlainCstInsn.java | 70 return new PlainCstInsn(getOpcode(), getPosition(), 81 return new PlainCstInsn(getOpcode(), getPosition(),
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